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1998 microchip technology inc. preliminary ds40192a-page 1 device included in this data sheet: pic16c505 high-performance risc cpu: only 33 instructions to learn operating speed: - dc - 20 mhz clock input - dc - 200 ns instruction cycle direct, indirect and relative addressing modes for data and instructions 12 bit wide instructions 8 bit wide data path 2-level deep hardware stack eight special function hardware registers direct, indirect and relative addressing modes for data and instructions all single cycle instructions (200 ns) except for program branches which are two-cycle peripheral features: 11 i/o pins with individual direction control 1 input pin high current sink/source for direct led drive timer0: 8-bit timer/counter with 8-bit programmable prescaler figure 1: pin diagram: device memory program data pic16c505 1024 x 12 72 x 8 pdip, soic, ceramic side brazed pic16c505 v dd rb5/osc1/clkin rb4/osc2/clkout rb3/mclr/v pp rc5/t0cki rc4 rc3 v ss rb0 rb1 rb2 rc0 rc1 rc2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 special microcontroller features: in-circuit serial programming (icsp) power-on reset (por) device reset timer (drt) watchdog timer (wdt) with dedicated on-chip rc oscillator for reliable operation programmable code protection internal weak pull-ups on i/o pins wake-up from sleep on pin change power-saving sleep mode selectable oscillator options: - intrc: precision internal 4 mhz oscillator - extrc: external low-cost rc oscillator - xt: standard crystal/resonator - hs: high speed crystal/resonator - lp: power saving, low frequency crystal cmos technology: low-power, high-speed cmos eprom technology fully static design wide operating voltage range (2.5v to 5.5v) wide temperature ranges - commercial: 0?c to +70?c - industrial: -40?c to +85?c - extended: -40?c to +125?c - < 1.0 m a typical standby current @ 5v low power consumption - < 2.0 ma @ 5v, 4 mhz - 15 m a typical @ 3.0v, 32 khz for tmr0 run- ning in sleep mode - < 1.0 m a typical standby current @ 5v pic16c505 14-pin, 8-bit cmos microcontroller
pic16c505 ds40192a -page 2 preliminary 1998 microchip technology inc. t able of contents 1.0 general description ............................................................................................................................... ...................................... 3 2.0 pic16c505 device varieties ............................................................................................................................... ........................ 5 3.0 architectural overview ............................................................................................................................... ................................. 7 4.0 m emory organizatio n ............................................................................................................................... ................................. 11 5.0 i/o por t ............................................................................................................................... ....................................................... 19 6.0 timer0 module and tmr0 register ............................................................................................................................... ........... 23 7.0 special features of the cpu ............................................................................................................................... ...................... 27 8.0 instruction set summary ............................................................................................................................... ............................ 39 9.0 development support ............................................................................................................................... ................................. 51 10.0 electrical characteristics - pic16c505 ............................................................................................................................... ...... 55 11.0 dc and ac characteristics - pic16c505 ............................................................................................................................... ... 65 12.0 packaging information ............................................................................................................................... ................................ 69 index ............................................................................................................................... ................................................................... 73 pic16c505 product identification system ............................................................................................................................... ............ 77 t o our v alued customers w e constantly str iv e to impro v e the quality of all our products and documentation. w e ha v e spent an e xceptional amount of time to ensure that these documents are correct. ho w e v er , w e realiz e that w e ma y ha v e missed a f e w things . if y ou nd an y inf or mation that is missing or appears in error , please use the reader response f or m in the bac k of this data sheet to inf or m us . w e appreciate y our assistance in making this a better document.
1998 microchip technology inc. preliminary ds40192a -page 3 pic16c505 1.0 g eneral description the pic16c505 from microchip t echnology is a lo w- cost, high perf or mance , 8-bit, fully static , epr om/ r om-based cmos microcontroller . i t emplo ys a risc architecture with only 33 single w ord/single cycle instr uctions . all instr uctions are single cycle ( 1 m s ) e xcept f or prog r am br anches which tak e tw o cycles . the pic16c505 deliv ers perf or mance an order of mag- nitude higher than its competitors in the same pr ice cat- egor y . the 12-bit wide instr uctions are highly symmetr ical resulting in 2:1 code compression o v er other 8-bit microcontrollers in its class . the easy to use and easy to remember instr uction set reduces de v elopment time signi cantly . the pic16c505 product is equipped with special f ea- tures that reduce system cost and po w er requirements . the p o w er-on reset (por) and de vice reset timer (dr t) eliminate the need f or e xter nal reset circuitr y . there are f iv e oscillator con gur ations to choose from, including intrc inter nal oscillator mode and t he po w er-sa ving lp (lo w p o w er) oscillator . p o w er sa ving sleep mode , w atchdog timer and code protection f eatures impro v e system cost, po w er and reliability . the pic1 6c505 is a v ailab le in the c ost-eff ectiv e one- time-prog r ammab le (o tp) v ersion , which is suitab le f or production in an y v olume . the customer can tak e full adv antage of microchip s pr ice leadership in o tp microcontrollers while bene ting from the o tp s e xibility . the pic16c505 product is suppor ted b y a full-f eatured macro assemb ler , a softw are sim ulator , an in-circuit em ulator , a ? compiler , a lo w-cost de v elopment pro- g r ammer , and a full f eatured prog r ammer . all the tools are suppor ted on ibm pc and compatib le machines . 1.1 applications the pic16c505 ts perf ectly in applications r anging from personal care appliances and secur ity systems to l o w-po w er remote tr ansmitters/receiv ers . the epr om technology mak es customizing application prog r ams (tr ansmitter codes , appliance settings , receiv er fre- quencies , etc.) e xtremely f ast and con v enient. the small f ootpr int pac kages , f or through hole or surf ace mounting, mak e this microcontroller perf ect f or applica- tions with space limitations . lo w-cost, lo w-po w er , high perf or mance , ease of use and i/o e xibility mak e the pic16c505 v er y v ersatile e v en in areas where no microcontroller use has been considered bef ore (e .g., timer functions , replacement of ?lue logic and pld s in larger systems , coprocessor applications).
pic16c505 ds40192a -page 4 preliminary 1998 microchip technology inc. t ab le 1-1: pic16c505 de vice pic16c505 clock maximum frequency of operation (mhz) 20 memory eprom program memory 1024 data memory (bytes) 72 peripherals timer module(s) tmr0 wake-up from sleep on pin change yes features i/o pins 11 input pins 1 internal pull-ups yes in-circuit serial programming yes number of instructions 33 packages 14-pin dip, soic, jw the pic16c505 de vice has p o w er-on reset, selectab le w atchdog timer , selectab le code protect, high i/o current capability and precision inter nal oscillator . the pic16c505 de vice uses ser ial prog r amming with data pin rb0 and cloc k pin rb1.
1998 microchip technology inc. preliminary ds40192a -page 5 pic16c505 2.0 pic16c505 de vice v arieties a v ar iety of p ac kaging options are a v ailab le . depending on application and production requirements , the proper de vice option can be selected using the inf or mation in this section. when placing orders , please use the pic16c505 product identi cation system at the bac k of this data sheet to specify the correct par t n umber . 2.1 uv erasab le de vices the uv er asab le v ersion, off ered in cer amic side br az ed pac kage , is optimal f or prototype de v elopment and pilot prog r ams . the uv er asab le v ersion can be er ased and reprog r ammed to an y of the con gur ation modes . microchip's picst ar t a plus and pr o ma te a pro- g r ammers all suppor t prog r amming of the pic16c505 . third par ty prog r ammers also are a v ailab le; ref er to the microchip third p ar ty guide f or a list of sources . 2.2 one-time-pr ogrammab le (o tp) de vices the a v ailability of o tp de vices is especially useful f or customers who need the e xibility f or frequent code updates or small v olume applications . the o tp de vices , pac kaged in plastic pac kages per mit the user to prog r am them once . i n addition to the prog r am memor y , the con gur ation bits m ust also be prog r ammed. note: please note that er asing the de vice will also er ase the pre- prog r ammed inter nal calibr ation v alue f or the inter nal oscillator . the calibr ation v alue m ust be sa v ed pr ior to e r asing the par t. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip o ff ers a qtp prog r amming ser vice f or f actor y production orders . t his ser vice is made a v ailab le f or users who cho o se not to prog r am a medium to high quantity of units and whose code patter ns ha v e stabiliz ed. t he de vices are identical to the o tp de vices b ut with all epr om locations and fuse options already prog r ammed b y the f actor y . cer tain code and prototype v er i cation procedures do apply bef ore production shipments are a v ailab le . please con- tact y our local microchip t echnology sales of ce f or more details . 2.4 serializ ed quic k-t urnar ound pr oduction (sqtp sm ) de vices microchip o ff ers a u nique prog r amming ser vice where a f e w user-de ned locations in each de vice are prog r ammed with diff erent ser ial n umbers . t he ser ial n umbers ma y be r andom, pseudo-r andom or sequential. ser ial prog r amming allo ws each de vice to ha v e a unique n umber which can ser v e as an entr y-code , pass w ord or id n umber .
pic16c505 ds40192a -page 6 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40192a -page 7 pic16c505 3.0 ar c hitectural over vie w the high perf or mance of the pic16c505 can be attr ib uted to a n umber of architectur al f eatures commonly f ound in risc microprocessors . t o begin with, the pic16c505 uses a har v ard architecture in which prog r am and data are accessed on separ ate b uses . this impro v es bandwidth o v er tr aditional v on neumann architecture where prog r am and data are f etched on the same b us . separ ating prog r am and data memor y fur ther allo ws instr uctions to be siz ed diff erently than the 8-bit wide data w ord. instr uction opcodes are 12-bit s wide , making it possib le to ha v e all single w ord instr uctions . a 12-bit wide prog r am memor y access b us f etches a 12-bit instr uction in a single cycle . a tw o-stage pipeline o v er laps f etch and e x ecution of instr uctions . consequently , all instr uctions ( 33 ) e x ecute in a single cycle ( 200n s @ 20 mh z ) e xcept f or prog r am br anches . t he pic1 6c505 a ddresses 1k x 12 of prog r am memor y . all prog r am memor y is inter nal. the pic16c505 can directly or indirectly address its register les and data memor y . all special function registers , including the prog r am counter , are mapped in the data memor y . the pic16c505 has a highly or thogonal (symmetr ical) instr uction set that mak es it possib le to carr y out an y oper ation on an y register using an y addressing mode . this symmetr ical nature and lac k of ?pecial optimal situations mak e prog r amming with the pic16c505 simple y et ef cient. in addition, the lear ning cur v e is reduced signi cantly . the pic16c505 de vice contains an 8-bit alu and w or king register . the alu is a gener al pur pose ar ithmetic unit. it perf or ms ar ithmetic and boolean functions betw een data in the w or king register and an y register le . the alu is 8-bits wide and capab le of addition, subtr action, shift and logical oper ations . unless otherwise mentioned, ar ithmetic oper ations are tw o's complement in nature . in tw o-oper and instr uctions , typically one oper and is the w (w or king) register . the other oper and is either a le register or an immediate constant. in single oper and instr uctions , the oper and is either the w register or a le register . the w register is an 8-bit w or king register used f or alu oper ations . it is not an addressab le register . depending on the instr uction e x ecuted, the alu ma y aff ect the v alues of the carr y (c), digit carr y (dc), and zero (z) bits in the st a tus register . the c and dc bits oper ate as a borr o w and digit borr o w out bit, respectiv ely , in subtr action. see the subwf and addwf instr uctions f or e xamples . a simpli ed b loc k diag r am is sho wn in figure 3-1 , with the corresponding de vice pins descr ibed in t ab le 3-1 .
pic16c505 ds40192a -page 8 preliminary 1998 microchip technology inc. figure 3-1: pic16c505 bloc k dia gram de vice reset timer p o w er-on reset w atchdog timer epr om prog r am memor y 12 data bus 8 12 prog r am bus instr uction reg prog r am counter ram file registers direct addr 5 ram addr 9 addr mux indirect addr fsr reg st a tus reg mux alu w reg instr uction decode & control timing gener ation osc1/clkin osc2 mclr vdd, vss timer0 por tb 8 8 rb4/osc2/clk out rb3/mclr/vpp rb2 rb1 rb0 5-7 3 rb5/osc1/clkin st a ck1 st a ck2 1k x 12 72 b ytes inter nal rc osc por tc rc4 rc3 rc2 rc1 rc0 rc5/t0cki
1998 microchip technology inc. preliminary ds40192a -page 9 pic16c505 t ab le 3-1: pic16c505 pinout description name dip pin # soic pin # i/o/p t ype buff er t ype description rb0 13 13 i/o ttl/st bi-directional i/o por t/ ser ial prog r amming data. can be softw are prog r ammed f or inter nal w eak pull-up and w ak e-up from sleep on pin change . this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . rb1 12 12 i/o ttl/st bi-directional i/o por t/ ser ial prog r amming cloc k. can be softw are prog r ammed f or inter nal w eak pull-up and w ak e-up from sleep on pin change . this b uff er is a schmitt t r igger input when used in ser ial prog r amming mode . rb2 11 11 i/o ttl bi-directional i/o por t. rc0 10 10 i/o ttl bi-directional i/o por t. rc1 9 9 i/o ttl bi-directional i/o por t. rc2 8 8 i/o ttl bi-directional i/o por t. rc3 7 7 i/o ttl bi-directional i/o por t. rc4 6 6 i/o ttl bi-directional i/o por t. rc5/t0cki 5 5 i/o st bi-directional i/o por t. can be con gured as t0cki. rb3/ mclr /v pp 4 4 i ttl input por t/master clear (reset) input/prog r amming v olt- age input. when con gured as mclr , this pin is an activ e lo w reset to the de vice . v oltage on mclr /v pp m ust not e xceed v dd dur ing nor mal de vice oper ation. can be softw are prog r a mmed f or inter nal w eak pull-up and w ak e-up from sleep on pin change . w eak pull- up only when con gured as rb3. rb4/osc2/clk out 3 3 i/o ttl bi-directional i/o por t/oscillator cr ystal output. con- nections to cr ystal or resonator in cr ystal oscillator mode (xt and lp modes only , rb4 in other modes). can be softw are prog r ammed f or inter nal w eak pull-up and w ak e-up from sleep on pin change . in extrc and intrc modes , the pin output can be con gured to clk out , which has 1/4 the frequency of osc1 and denotes the instr uction cycle r ate . rb5/osc1/clkin 2 2 i /o ttl/st bidirectional io por t/oscillator cr ystal input/e xter nal cloc k source input (rb5 in inter nal rc mode only , osc1 in all other oscillator modes). ttl input when rb5, st input in e xter nal rc oscillator mode . v dd 1 1 p p ositiv e supply f or logic and i/o pins v ss 14 14 p ground ref erence f or logic and i/o pins legend: i = input, o = output, i/o = input/output, p = po w er , ?= not used, ttl = ttl input, st = schmitt t r igger input
pic16c505 ds40192a -page 10 preliminary 1998 microchip technology inc. 3.1 cloc king sc heme/ instruction cyc le the cloc k input (osc1/clkin pin) is inter nally divided b y f our to gener ate f our non-o v er lapping quadr ature cloc ks namely q1, q2, q3 and q4. inter nally , the prog r am counter is incremented e v er y q1, and the instr uction is f etched from prog r am memor y and latched into instr uction register in q4. it is decoded and e x ecuted dur ing the f ollo wing q1 through q4. the cloc ks and instr uction e x ecution o w is sho wn in figure 3-2 and example 3-1 . 3.2 instruction flo w/pipelining an instr uction cycle consists of f our q cycles (q1, q2, q3 and q4). the instr uction f etch and e x ecute are pipelined such that f etch tak es one instr uction cycle while decode and e x ecute tak es another instr uction cycle . ho w e v er , due to the pipelining, each instr uction eff ectiv ely e x ecutes in one cycle . if an instr uction causes the prog r am counter to change (e .g., goto ) then tw o cycles are required to complete the instr uction ( example 3-1 ). a f etch cycle begins with the prog r am counter (pc) incrementing in q1. in the e x ecution cycle , the f etched instr uction is latched into the instr uction register (ir) in cycle q1. this instr uction is then decoded and e x ecuted dur ing the q2, q3, and q4 cycles . data memor y is read dur ing q2 (oper and read) and wr itten dur ing q4 (destination wr ite). figure 3-2: cloc k/instruction cyc le example 3-1: instruction pipeline flo w q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc pc pc+1 pc+2 f etch inst (pc) ex ecute inst (pc-1) f etch inst (pc+1) ex ecute inst (pc) f etch inst (pc+2) ex ecute inst (pc+1) inter nal phase cloc k all instr uctions are single cycle , e xcept f or an y prog r am br anches . these tak e tw o cycles since the f etch instr uction is ushed from the pipeline while the ne w instr uction is being f etched and then e x ecuted. 1. movlw 03h f etch 1 ex ecute 1 2. movwf portb f etch 2 ex ecute 2 3. call sub_1 f etch 3 ex ecute 3 4. bsf portb , bit 1 f etch 4 flush f etch sub_1 ex ecute sub_1
1998 microchip technology inc. preliminary ds40192a -page 11 pic16c505 4.0 m emor y or ganizatio n pic1 6 c5 05 memor y is organiz ed into prog r am mem- or y and data memor y . f or the pic16c505, a paging scheme is used. prog r am memor y pages are accessed using one s t a tus register bit. data memor y banks are accessed using the file sel ect re gister (fsr). 4.1 pr ogram memor y or ganization the pic16 c5 05 de vices ha v e a 12-bit prog r am counter (pc). t he 1k x 12 (0000h-03ffh) f or the pic1 6 c50 5 are ph ysically implemented. ref er to figure 4-1 . accessing a location abo v e th is boundar y will cause a wr ap-around within the rst 1k x 12 space . the eff ectiv e reset v ector is at 0 000h , (see figure 4-1 ) . location 03ffh (pic1 6 c50 5 ) contains the inter nal cloc k oscillator calibr ation v alue . this v alue should ne v er be o v erwr itten . figure 4-1: pr ogram memor y map and stac k f or the pic16c505 call, retlw pc<11:0> stac k le v el 1 stac k le v el 2 user memor y space 12 0000h 7ffh 01ffh 0200h reset v ector (note 1) note 1: address 0000h becomes the eff ectiv e reset v ector . location 03ffh (pic1 6 c50 5 ) contains t he movlw xx int ernal r c oscillato r c alibr ation v alue . 1024 w ord 03ffh 0400h on-chip prog r am memor y
pic16c505 ds40192a -page 12 preliminary 1998 microchip technology inc. 4.2 data memor y or ganization data memor y is composed of registers , or b ytes of ram. theref ore , data memor y f or a de vice is speci ed b y its register le . the register le is divided into tw o functional g roups: special function registers and gener al pur pose registers . the special function registers include the tmr0 register , the prog r am counter (pc), the status register , the i/o registers (por ts), and the file select register (fsr). in addition, special pur pose registers are used to control the i/o por t con gur ation and prescaler options . the gener al pur pose registers are used f or data and control inf or mation under command of the instr uctions . f or the pic1 6 c50 5 , the register le is composed of 8 special function registers , 2 4 g ener al pur pose registers , and 48 g ener al pur pose registers that ma y be addressed using a banking scheme ( figure 4-2 ). 4.2.1 gener al pur pose register file the ge ner al pur pos e register le is accessed either directly or indirectly through the le select register fsr ( section 4.8 ). figure 4-2: pic16c505 register file map file address 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 1f h i ndf ( 1) tmr0 pcl st a tus fsr osccal por tb 0f h 10 h bank 0 bank 1 3f h 30 h 20 h 2f h gener al pur pose register s gener al pur pose register s gener al pur pose register s addresses map bac k to addresses in bank 0. note 1: not a ph ysical register . f sr<6:5> 00 0 1 bank 3 7fh 70h 60h 6fh gener al pur pose register s 11 bank 2 5fh 50h 40h 4fh gener al pur pose register s 10 08h por tc
1998 microchip technology inc. preliminary ds40192a -page 13 pic16c505 4.2.2 special function registers the special function registers (sfrs) are registers used b y the cpu and per ipher al functions to control the oper ation of the de vice ( t ab le 4-1 ). t he special registers can be classi ed into tw o sets . the special function registers associated with the ?ore functions are descr ibed in this section. those related to the oper ation of the per ipher al f eatures are descr ibed in the section f or each per ipher al f eature . t ab le 4-1: special function register (sfr) summar y ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue o n p o wer -o n r eset v alue o n m clr an d w dt reset v alue on w ake-up on pin c hang e 00h indf uses contents of fsr to address data memor y (not a ph ysical register) xxxx xxxx uuuu uuuu uuuu uuuu 01h tmr0 8-bit real-time cloc k/counter xxxx xxxx uuuu uuuu uuuu uuuu 02h (1) pcl lo w order 8 bits of pc 1111 1111 1111 1111 1111 1111 03h st a tus rbwuf p a o t o pd z dc c 0001 1xxx 000q quuu 100q quuu 04h fsr indirect data memor y address pointer 110x xxxx 11uu uuuu 11uu uuuu 05h osccal cal5 cal4 cal3 cal2 cal1 cal0 1000 00-- uuuu uu-- uuuu uu-- n/a trisb i/o control registers --11 1111 --11 1111 --11 1111 n/a trisc i/o control registers --11 1111 --11 1111 --11 1111 n/a option rbwu rbpu t ocs t ose psa ps2 ps1 ps0 1111 1111 1111 1111 1111 1111 06h por tb rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu --uu uuuu 07h por tc rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu --uu uuuu legend: shaded cellls not used b y p or t registers , read as ?? = unimplemented, read as ?? x = unkno wn, u = unchanged.
pic16c505 ds40192a -page 14 preliminary 1998 microchip technology inc. 4.3 s t a tus register this register contains the ar ithmetic status of the alu , the reset status , and the page preselect bit. the st a tus register can be the destination f or an y instr uction, as with an y other register . if the st a tus register is the destination f or an instr uction that aff ects the z, dc or c bits , then the wr ite to these three bits is disab led. these bits are set or cleared according to the de vice logic. fur ther more , the t o and pd bits are not wr itab le . theref ore , the result of an instr uction with the st a tus register as destination ma y be diff erent than intended. f or e xample , clrf status will clear the upper three bits and set the z bit. this lea v es the st a tus register as 000u u1uu (where u = unchanged). it is recommended, theref ore , that only bcf , bsf and movwf instr uctions be used to alter the st a tus register because these instr uctions do not aff ect the z, dc or c bits from the st a tus register . f or other instr uctions , which do aff ect st a tus bits , see instr uction set summar y . figure 4-3: st a tus register (ad dress:03 h ) r/w - 0 r/w - 0 r/w - 0 r- 1 r- 1 r/w - x r/w - x r/w - x rb wuf p a0 t o pd z dc c r = readab le bit w = wr itab le bi t - n = v alue at por reset bit7 6 5 4 3 2 1 bit0 bit 7: rb wuf : io reset bit 1 = reset due to w ak e-up from sleep o n p in change 0 = after po w er up or other reset bit 6 : unimplemented bit 5: p a0 : prog r am page preselect bit s 1 = p age 1 (200h - 3ffh) 0 = p age 0 (000h - 1ffh) each page is 512 b ytes . using the p a0 bit as a gener al pur pose read/wr ite bit i n de vices which do not use it f or prog r am p age preselect i s not recommended since this ma y aff ect upw ard compatibility with future products . bit 4: t o : time-out bit 1 = after po w er-up , clrwdt instr uction, or sleep instr uction 0 = a wdt time-out occurred bit 3: pd : p o w er-do wn bit 1 = after po w er-up or b y the clrwdt instr uction 0 = by e x ecution of the sleep instr uction bit 2: z : zero bit 1 = the result of an ar ithmetic or logic oper ation is z ero 0 = the result of an ar ithmetic or logic oper ation is not z ero bit 1: dc : digit carr y/ borro w bit (f or addwf and subwf i nstr uctions) add wf 1 = a carr y f rom the 4th lo w order bit of the result occurred 0 = a c arr y f rom the 4th lo w order bit of the resul t did not occur subwf 1 = a borro w from the 4th lo w order bit of the result did not occur 0 = a borro w from the 4th lo w order bit of the result occurred bit 0: c : carr y/ borro w bit (f or addwf , subwf and rrf , rlf i nstr uctions ) add wf subwf rrf or rlf 1 = a carr y occurred 1 = a borro w did not occur load bit with ls b o r ms b , respectiv ely 0 = a carr y did not occur 0 = a borro w occurred
1998 microchip technology inc. preliminary ds40192a -page 15 pic16c505 4.4 o ption register the option register is a 8-bit wide , wr ite-only register which contains v ar ious control bits to con gure the t imer0/wdt prescaler and t imer0 . by e x ecuting the option instr uction, the contents of the w register will be tr ansf erred to the option register . a reset sets the optio n<7: 0> bits . note: if tris bit is set to ?? the w ak e-up on change and pull-up functions are disab led f or that pin; i.e ., note that tris o v err ides option control of rbpu and rbwu . figure 4-4: option register w - 1 w - 1 w - 1 w - 1 w - 1 w - 1 w - 1 w - 1 rb wu rb pu t0cs t0 se psa ps2 ps1 ps0 w = wr itab le bit u = unimplemented bit - n = v alue at por reset ref erence t ab le 4-1 f or other resets . bit7 6 5 4 3 2 1 bit0 bit 7 : rbwu : enab le w ak e-up o n pin change ( rb 0, rb 1 , rb 3 , rb4 ) 1 = disab led 0 = enab led bit 6 : rbpu : enab le w eak pull-ups ( rb0, rb1, rb3, rb4 ) 1 = disab led 0 = enab led bit 5 : t0cs : timer0 cloc k source select bi t 1 = t r ansition on t0cki pin 0 = t r ansition on inter nal instr uction cycle cloc k, f osc/4 bit 4 : t0se : timer0 source edge select bit 1 = i ncrement on high to lo w tr ansition on the t0cki pin 0 = increment on lo w to high tr ansition on the t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to t imer0 bit 2-0: ps2:ps0 : prescaler r ate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit v alue t imer0 rate wdt rate
pic16c505 ds40192a -page 16 preliminary 1998 microchip technology inc. 4.5 osccal register the oscillator calibr ation (osccal) register is used to calibr ate the inter nal 4 mhz oscillator . it contains six bits f or ne calibr ation. figure 4-5: osccal regi ster (ad dress 05 h )pic16c505 r/w -1 r/w -0 r/w -0 r/w -0 r/w -0 r/w -0 u- 0 u-0 cal5 cal4 cal3 cal2 cal1 cal0 r = readab le bit w = wr itab le bit u = unimplemented bit, re ad as ? - n = v alue at por reset bit7 bit0 bit 7-4: cal<5:0>: fine calibr ation
1998 microchip technology inc. preliminary ds40192a -page 17 pic16c505 4.6 pr ogram counter as a prog r am instr uction is e x ecuted, the prog r am counter ( pc) will contain the address of the ne xt prog r am instr uction to be e x ecuted. the pc v alue is increased b y one e v er y instr uction cycle , unless an instr uction changes the pc . f or a goto instr uction, bits 8:0 of the pc are pro vided b y the goto instr uction w ord. the pc latch (pcl) is mapped to pc<7:0> . bit 5 of the st a tus register pro vides page inf or mation to bit 9 of the pc ( figure 4- 6 ) . f or a call instr uction, or an y instr uction where the pcl is the destination, bits 7:0 of the pc again are pro vided b y the instr uction w ord. ho w e v er , pc<8> does not come from the instr uction w ord, b ut is alw a ys cleared ( figure 4-6 ) . instr uctions where the pcl is the destination, or modify pcl instr uctions , include movwf pc, addwf pc, and bsf pc,5. figure 4-6: loading of pc branc h instructions - pic16c505 note: because pc<8> is cleared in the call instr uction, or an y modify pcl instr uction, all subroutine calls or computed jumps are limited to the rst 256 locations of an y pro- g r am memor y page (512 w ords long). p a0 st a tus pc 8 7 0 pcl 9 10 i n str uction w o rd 7 0 goto instruction call or modify pcl instruction 11 p a0 st a tus pc 8 7 0 pcl 9 10 i n str uction w o rd 7 0 11 reset to ? 4.6.1 eff ects of reset the prog r am counter is set upon a reset , which means that the pc addresses the last location in the last page i.e ., the oscillator calibr ation instr uction . a fter e x ecuting m o v l w xx, the pc w ill roll o v er to location 00h, and begin e x ecuting user code . the st a tus register page preselect bits are cleared upon a reset , which means that page 0 is pre- selected. theref ore , upon a reset , a goto instr uction will automatically cause the prog r am to jump to page 0 until the v alue of the page bits is altered. 4.7 s tac k pic16 c5 05 de vices ha v e a 1 2- bit wide hardw are push/pop stac k. a call instr uction will push the current v alue of stac k 1 into stac k 2 and then push the current prog r am counter v alue , incremented b y one , into stac k le v el 1. if more than tw o sequential call s are e x ecuted, only the most recent tw o retur n addresses are stored. a retlw instr uction will pop the contents of stac k le v el 1 into the prog r am counter and then cop y stac k le v el 2 contents into le v el 1. if more than tw o sequential retlw s are e x ecuted, the stac k will be f illed with the address pre viously stored in le v el 2. note that the w register will be loaded with the liter al v alue speci ed in the instr uction. this is par ticular ly useful f or the implementation of data look-up tab les within the prog r am memor y .
pic16c505 ds40192a -page 18 preliminary 1998 microchip technology inc. 4.8 indirect data ad dressing; indf and fsr register s the indf register is not a ph ysical register . addressing indf actually addresses the register whose address is contained in the fsr register ( fsr is a pointer ). this is indirect addressing. example 4-1: indirect ad dressing register le 0 7 c ontains the v alue 10h register le 0 8 c ontains the v alue 0ah load the v alue 0 7 i nto the fsr register a read of the indf register will retur n the v alue of 10h increment the v alue of the fsr register b y one (fsr = 0 8) a read of the indr register no w will retur n the v alue of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. wr iting to the indf register indirectly results in a no-oper ation (although st a tus bits ma y be aff ected). a simple prog r am to clear ram locations 10h-1fh using indirect addressing is sho wn in example 4-2 . example 4-2: ho w t o clear ram using indirect ad dressing movlw 0x10 ; initialize pointer movwf fsr ; to ram next clrf indf ; clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is a 5-bit wide register . it is used in conjunction with the indf register to indirectly address the data memor y area. the fsr<4:0> bits are used to select data memor y addresses 00h to 1fh. the de vice u ses fsr 6:5 to s elect betw een bank s 0 :3 . figure 4-7: direct/indirect ad dressing note 1: f or register map detail see section 4.2 . direct addressing (fsr) 6 5 4 (opcode) 0 bank select location select 00 01 10 11 00h 0fh 10h data memor y(1) 1fh 3fh 5fh 7fh bank 0 bank 1 bank 2 bank 3 addresses map bac k to addresses in bank 0. indirect addressing 6 5 4 (fsr) 0 bank location select
1998 microchip technology inc. preliminary ds40192a -page 19 pic16c505 5.0 i/o p or t as with an y other register , the i/o register c an be wr itten and read under prog r am control. ho w e v er , read instr uctions (e .g., movf portb,w ) alw a ys read the i/o pins independent of the pin s input/output modes . on reset , all i/o por ts are de ned as input (inputs are at hi-impedance) since the i/o control registers are all set. 5.1 por tb por tb is an 8-bit i/o register . only the lo w order 6 bits are used ( rb 5: rb 0). bits 7 and 6 are unimplemented and read as '0's . please note that rb 3 is an input only pin . the con gur ation w ord can set se v er al i/o s to alter nate functions . when acting as alter nate functions the pins will read as ? dur ing por t read. pins rb0, rb1, rb3 and rb4 can be con gured with w eak pull-ups and also with w ak e-up on change . the w ak e-up on change and w eak pull-up functions are not pin selectab le . if pin 4 is con gured as mclr , w eak pull-up is alw a ys o ff and w ak e-up on change f or this pin is not enab led. 5.2 por tc por tc is an 8-bit i/o register . only the lo w order 6 bits are used (rc5:rc0). bits 7 and 6 are unimple- mented and read as ? s . 5.3 tris register s the output dr iv er control registe r is loaded with the contents of the w register b y e x ecuting the tris f instr uction. a '1' from a tris register bit puts the corresponding output dr iv er in a hi-impedance mode . a '0' puts the contents of the output data latch on the selected pins , enab ling the output b uff er . the e xception s are rb 3 which is input only and rc5 which ma y be controlled b y the option register , see figure 4- 4 . the tris registers are ?r ite-only and are set (output dr iv ers disab led) upon reset . note: a read of the por ts reads the pins , not the output data latches . that is , if an output dr iv er on a pin is enab led and dr iv en high, b ut the e xter nal system is holding it lo w , a read of the por t will indicate that the pin is lo w . 5.4 i/o interfacing the equiv alent circuit f or an i/o por t pin is sho wn in figure 5-1 . all por t pin s , e xcept rb 3 which is input only , m a y be used f or both input and output oper ations . f or input oper ations these por ts are non- latching. an y input m ust be present until read b y an input instr uction (e .g., movf portb, w ). the outputs are latched and remain unchanged until the output latch is re wr itten. t o use a por t pin as output, the corresponding direction control bit in tris m ust be cleared (= 0). f or use as an input, the corresponding tris bit m ust be set. an y i/o pin (e xcept rb 3) c an be prog r ammed individually as input or output. figure 5-1: equiv alent cir cuit f or a single i/o pin note 1: i/o pins ha v e protection diodes to v dd and v ss . data bu s q d q ck q d q ck p n wr p or t tris ? data tris rd p or t v ss v dd i/o p in (1) w reg l atch l atch reset
pic16c505 ds40192a -page 20 preliminary 1998 microchip technology inc. t ab le 5-1: summar y of p or t register s ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue on p o wer -on reset v alue on mclr and wdt reset v alue on w ake-up on pin chang e n/a trisb i/o control registers --11 1111 --11 1111 --11 1111 n/a trisc i/o control registers --11 1111 --11 1111 --11 1111 n/a option rbwu rbpu t ocs t ose psa ps2 ps1 ps0 1111 1111 1111 1111 1111 1111 03h st a tus rbwuf p a o t o pd z dc c 0001 1xxx 000q quuu 100q quuu 06h por tb rb5 rb4 rb3 rb2 rb1 rb0 --xx xxxx --uu uuuu --uu uuuu 07h por tc rc5 rc4 rc3 rc2 rc1 rc0 --xx xxxx --uu uuuu --uu uuuu legend: shaded cellls not used b y p or t registers , read as ?? = unimplemented, read as ?? x = unkno wn, u = unchanged. 5.5 i/o pr ogramming considerations 5.5.1 bi-directional i/o p or ts some instr uctions oper ate inter nally as read f ollo w ed b y wr ite oper ations . the bcf and bsf instr uctions , f or e xample , read the entire por t into the cpu , e x ecute the bit oper ation and re-wr ite the result. caution m ust be used when these instr uctions are applied to a por t where one or more pins are used as input/outputs . f or e xample , a bsf oper ation on bit5 of por tb will cause all eight bits of por tb to be read into the cpu , bit5 to be set and the por tb v alue to be wr itten to the output latches . if another bit of por tb is used as a bi- directional i/o pin (sa y bit0) and it is de ned as an input at this time , the input signal present on the pin itself w ould be read into the cpu and re wr itten to the data latch of this par ticular pin, o v erwr iting the pre vious content. as long as the pin sta ys in the input mode , no prob lem occurs . ho w e v er , if bit0 is s witched into output mode later on, the content of the data latch ma y no w be unkno wn. example 5-1 sho ws the eff ect of tw o sequential read- modify-wr ite instr uctions (e .g., bcf, bsf , etc.) on an i/ o por t. a pin activ ely outputting a high or a lo w should not be dr iv en from e xter nal de vices at the same time in order to change the le v el on this pin (?ired-or? ?ired- and?. the resulting high output currents ma y damage the chip . example 5-1: read- modify-write instructions on an i/o p or t ;initial portb settings ; portb< 5: 3> inputs ; portb< 2: 0> outputs ; ; portb latch portb pins ; ---------- ---------- bcf portb, 5 ;--01 -p pp --11 p ppp bcf portb, 4 ;--10 -p pp --11 p ppp movlw 0 0 7h ; tris portb ; --10 -p pp --11 p ppp ; ;note that the user may have expected the pin ;values to be --00 p ppp. the 2nd bcf caused ;rb5 t o be latched as the pin value (high). 5.5.2 successiv e oper ations on i/o p or ts the actual wr ite to an i/o por t happens at the end of an instr uction cycle , whereas f or reading, the data m ust be v alid at the beginning of the instr uction cycle ( figure 5-2 ). theref ore , care m ust be e x ercised if a wr ite f ollo w ed b y a read oper ation is carr ied out on the same i/o por t. the sequence of instr uctions should allo w the pin v oltage to stabiliz e (load dependent) bef ore the ne xt instr uction, which causes that le to be read into the cpu , is e x ecuted. otherwise , the pre vious state of that pin ma y be read into the cpu r ather than the ne w state . when in doubt, it is better to separ ate these instr uctions with a nop or another instr uction not accessing this i/o por t.
1998 microchip technology inc. preliminary ds40192a -page 21 pic16c505 figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instr uction f etched rb5:rb0 mo vwf por tb nop p or t pin sampled here nop mo vf por tb ,w instr uction e x ecuted mo vwf por tb (wr ite to por tb) nop mo vf por tb ,w this e xample sho ws a wr ite to por tb f ollo w ed b y a read from por tb . data setup time = (0.25 t cy ? t pd ) where: t cy = instr uction cycle . t pd = propagation dela y theref ore , at higher cloc k frequencies , a wr ite f ollo w ed b y a read ma y be prob lematic. (read por tb) p or t pin wr itten h ere
pic16c505 ds40192a -page 22 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40192a -page 23 pic16c505 6.0 timer0 module and tmr0 register the timer0 module has the f ollo wing f eatures: 8-bit timer/counter register , tmr0 - readab le and wr itab le 8-bit softw are prog r ammab le prescaler inter nal or e xter nal cloc k select - edge select f or e xter nal cloc k figure 6-1 is a simpli ed b loc k diag r am of the t imer0 module . timer mode is selected b y clear ing the t0 c s b it (option<5>). i n timer mode , the t imer0 module will increment e v er y instr uction cycle (without prescaler). if tmr0 register is wr itten, the increment is inhibited f or the f ollo wing tw o cycles ( figure 6-2 and figure 6-3 ). t he user can w or k around this b y wr iting an adjusted v alue to the tmr0 register . counter mode is selected b y setting the t0cs bit (option<5>). in this mode , timer0 will increment either on e v er y r ising or f alling edge of pin t0cki. the t 0se bit (option<4>) deter mines the source edge . clear ing the t0se bit selects the r ising edge . restr ictions on the e xter nal cloc k input are discussed in detail in section 6.1 . the prescaler ma y be used b y either t he t imer0 module or t he w a tchdog ti mer , b ut not both . t he prescaler assignment is controlled in softw are b y the control bit p sa (option<3>). c lear ing the psa bit will assign the prescaler to t imer0 . t he prescaler is n ot r eadab le o r wr itab le . w hen the prescaler is assigned to the timer0 module , prescale v alues of 1:2, 1:4, . .., 1:256 are selectab le . section 6.2 details the oper ation of the prescaler . a summar y of registers associated with the timer0 module is f ound in t ab le 6-1 . figure 6-1: t imer0 bloc k dia gram note 1: b its t 0 cs , t0 se, p sa, ps2, ps1 and ps0 are located in the option register . 2: t he prescaler is shared with the w atchdog timer ( figure 6-5 ). 0 1 1 0 t0cs (1) f osc /4 prog r ammab le prescaler (2) sync with inter nal cl oc ks tmr0 reg psout (2 cycle dela y) psout data b us 8 psa (1) ps2, ps1, ps0 (1) 3 sync t 0se rc5 / t0 cki pin
pic16c505 ds40192a -page 24 preliminary 1998 microchip technology inc. figure 6-2: timer0 timing: internal cloc k/no prescale figure 6-3: timer0 timing: internal cloc k/prescale 1:2 t ab le 6-1: register s associated with timer0 ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue o n p o wer -o n r eset v alue o n m clr an d w dt reset v alue on w ake-up on pin c hang e 0 1 h tmr0 timer0 - 8-bit real-time cloc k/counter x xxx xxxx uuuu uuuu uuuu uuuu n /a option rb wu rb pu t0cs t0se psa ps2 ps1 ps0 1 1 11 1111 1111 1111 1111 1111 n/a trisb i/o control registers --11 1111 --11 1111 --11 1111 n/a trisc i/o control registers --11 1111 --11 1111 --11 1111 legend: shaded cells not used b y timer0, - = unimplemented, x = unkno wn, u = unchanged, pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instr uction ex ecuted pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (prog r am counter) instr uction f etch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 mo vwf tmr0 mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w mo vf tmr0,w wr ite tmr0 e x ecuted read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instr uction ex ecute t 0
1998 microchip technology inc. preliminary ds40192a -page 25 pic16c505 6.1 using t imer0 with an external cloc k when an e xter nal cloc k input is used f or t imer0 , it m ust meet cer tain requirements . the e xter nal cloc k requirement is due to i nter nal phase cloc k ( t osc ) synchronization. also , there is a dela y in the actual incrementing of t imer0 after synchronization. 6.1.1 exter nal cloc k synchronization when no prescaler is used, the e xter nal cloc k input is the same as the prescaler output. the sy nchroniz ation of t 0cki with the inter nal phase cloc ks is accomplished b y s ampling the prescaler output on the q2 and q4 cycles of the inter nal phase cloc ks ( figure 6-4 ). t heref ore , it is necessar y f or t0cki to be high f or at least 2 t osc (and a small rc dela y of 20 ns) and lo w f or at least 2 t osc ( and a small rc dela y of 20 ns) . r ef er to the e lectr ical speci cation of the desired de vice . when a prescaler is used, the e xter nal cloc k input is divided b y the asynchronous r ipple counter-type prescaler so that the prescaler output is symmetr ical. f or the e xter nal cloc k to meet the sampling requirement, the r ipple counter m ust be tak en into account. theref ore , it is necessar y f or t0cki to ha v e a per iod of at least 4 t osc (and a small rc dela y of 40 ns) divided b y the prescaler v alue . the only requirement on t0cki high and lo w time is that the y do not violate the minim um pulse width requirement of 10 ns . ref er to par ameters 40, 41 and 42 in the electr ical speci cation of the desired de vice . 6.1.2 t imer0 increment dela y since the prescaler output is synchroniz ed with the inter nal cloc ks , there is a small dela y from the time the e xter nal cloc k edge occurs to the time the t imer0 module is actually incremented. figure 6-4 sho ws the dela y from the e xter nal cloc k edge to the timer incrementing. figure 6-4: timer0 timing with external cloc k increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 t imer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2 : 3 : delay from clock input change to t imer0 increment is 3 tosc t o 7 tosc. (duration of q = tosc) . therefore, the error in measuring the interval between two edges on t imer0 input = 4 tosc m ax. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic16c505 ds40192a -page 26 preliminary 1998 microchip technology inc. 6.2 prescaler an 8-bit counter is a v ailab le as a prescaler f or the timer0 module , or as a postscaler f or the w atchdog timer (wdt), respectiv ely ( section 7.6 ). f or simplicity , this counter is being ref erred to as ?rescaler throughout this data sheet. note that the prescaler ma y be used b y either the timer0 module or the wdt , b ut not both. thus , a prescaler assignment f or the timer0 module means that there is no prescaler f or the wdt , and vice-v ersa. the psa and ps2:ps0 bits (option<3:0>) deter mine prescaler assignment and prescale r atio . when assigned to the timer0 module , all instr uctions wr iting to the tmr0 register (e .g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler . when assigned to wdt , a clrwdt instr uction will clear the prescaler along with the wdt . the prescaler is neither readab le nor wr itab le . on a reset , the prescaler contains all '0's . 6.2.1 s witching prescaler assignment the prescaler assignment is fully under softw are control (i.e ., it can be changed ?n the y dur ing prog r am e x ecution). t o a v oid an unintended de vice reset , the f ollo wing instr uction sequence ( example 6-1 ) m ust be e x ecuted when changing the prescaler assignment from timer0 to the wdt . example 6-1: changing prescaler (t imer0 ? wdt) 1. clrwdt ;clear wdt 2. clrf tmr0 ;clear tmr0 & prescaler 3. movlw '00xx1111? ; ;these 3 lines (5, 6, 7) 4. option ; are required only if ; desired 5. clrwdt ;ps<2:0> are 000 or 001 6. movlw '00xx1xxx? ;set postscaler to 7. option ; desired wdt rate t o change prescaler from the wdt to the timer0 m odule , use the sequence sho wn in example 6-2 . t his sequence m ust be used e v en if the wdt is disab led . a c lrwdt instr uction should be e x ecuted bef ore s witching the prescaler . example 6-2: changing prescaler (wdt ? t imer0 ) clrwdt ;clear wdt and ;prescaler movlw ' xxxx0xxx' ; select tmr0, new ; prescale value and ; clock source option figure 6-5: bloc k dia gram of the timer0/wdt prescaler t cy ( = f osc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m m ux w atchdog ti mer psa 0 1 0 1 wdt time- ou t ps2:ps0 8 note: t0 cs , t0 se, psa, ps2:ps0 are bits in the option register . psa wdt enab le bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x t 0se rc5 / t0cki pin
1998 microchip technology inc. preliminary ds40192a -page 27 pic16c505 7.0 special features of the cpu what sets a microcontroller apar t from other processors are special circuits to deal with the needs of real-time applications . the pic16c505 f amily of microcontrollers has a host of such f eatures intended to maximiz e system reliability , minimiz e cost through elimination of e xter nal components , pro vide po w er sa ving oper ating modes and off er code protection. these f eatures are: oscillator selection reset - p o w er-on reset (por) - de vice reset timer (dr t) - w ak e-up from sleep on p in change w atchdog timer (wdt) slee p c ode protection id locations in-circuit ser ial prog r amming cloc k out the pic16c505 has a w atchdog timer which can be shut off only through con gur ation bit wdte. it r uns off of its o wn rc oscillator f or added reliability . if using hs , xt or lp selectab le oscillator options , there is alw a ys an 18 ms (nominal) dela y pro vided b y the de vice reset timer (dr t), intended to k eep the chip in reset until the cr ystal oscillator is stab le . if using intrc or extrc there is an 18 ms dela y only on v dd po w er-up . with this timer on-chip , most applications need no e xter nal reset circuitr y . the sleep mode is designed to off er a v er y lo w current po w er-do wn mode . the user can w ak e-up from sleep through a change on input pins o r through a w atchdog timer time-out. se v er al oscillator options are also made a v ailab le to allo w the par t to t the application , including an inter nal 4 mhz oscillator . the extr c oscillator option sa v es system cost while the lp cr ystal option sa v es po w er . a set of con gur ation bits are used to select v ar ious options . 7.1 con guration bits the pic1 6 c5 05 con gur ation w ord consists of 6 b its . c on gur ation bits can be prog r ammed to select v ar ious de vice con gur ations . t hree bits are f or the selection of the oscillator type , o ne bit is the w atchdog timer enab le bit , and one bit is the mclr enab le bit. o ne bit is the code protection bit ( figure 7-1 ) . figure 7-1: configuration w or d f or pic16c505 cp cp cp cp cp cp mclre cp wdte fosc2 f os c1 f os c0 reg ist er : config address (2) : 0fffh bit11 10 9 8 7 6 5 4 3 2 1 bit0 bit 11-6, 4: cp code pr otection bits (1)(2) bit 5: mclre: rb3/ mclr pin function select 1 = rb3/ mclr pin function is mclr 0 = rb3/ mclr pin function is digital i/o , mclr inter nally tied to v dd bit 3: wdte : w atchdog timer enab le bit 1 = wdt enab led 0 = wdt disab led bit 2-0: fosc1:fosc0: oscillator selection bits 111 = e xter nal rc oscillator/clk out function on rb4/osc2/clk out pin 110 = e xter nal rc oscillator/rb4 function on rb4/osc2/clk out pin 101 = inter nal rc oscillator/clk out function on rb4/osc2/clk out pin 100 = inter nal rc oscillator/rb4 function on rb4/osc2/clk out pin 011 = in v alid selection 010 = hs oscillator 001 = xt oscillator 000 = lp oscillator note 1: 03ffh is alw a ys uncodepr totected on the pic16c505. this location contains the mo vl wxx calibr ation instr uction f or the intrc . note 2: ref er to the pic16c505 prog r amming speci cations to deter mine ho w to access the con- gur ation w ord. this register is not user addressab le dur ing de vice oper ation.
pic16c505 ds40192a -page 28 preliminary 1998 microchip technology inc. 7.2 oscillator con gurations 7.2.1 oscillator t ypes the pic16c505 can be oper ated in f our diff erent oscillator modes . the user can prog r am t hree con gur ation bits (fosc 2 :fosc0) to select one of these f our modes: lp: lo w p o w er cr ystal xt : cr ystal/resonator hs: high speed cr ystal/resonator intr c: inter nal 4 mhz oscillator extr c: exter nal resistor/capacitor 7.2.2 cr ystal oscillator / cer amic resonators in hs , xt or l p m odes , a cr ystal or cer amic resonator is c onnected to the rb 5/ osc1/clkin and rb 4/ osc2 /clk out pins to estab lish oscillation ( figure 7- 2 ). the pic16c505 oscillator design requires the use of a par allel cut cr ystal. use of a ser ies cut cr ystal ma y giv e a frequency out of the cr ystal man uf acturers speci cations . when in hs , xt o r lp modes , the de vice can ha v e an e xter nal cloc k source dr iv e the rb 5/ osc1/clkin pin ( figure 7-3 ). figure 7-2: cr ystal operation (or ceramic resonator) (hs, x t or lp osc configuration) figure 7-3: external cloc k input operation (hs, x t or lp osc configuration) note 1: see capacitor selection tab les f or recommended v alues of c1 and c2. 2: a ser ies resistor (rs) ma y be required f or a t str ip cut cr ystals . 3: rf v ar ies with the cr ystal chosen (appro x. v alue = 10 m w ). c1 (1) c2 (1) xt al osc2 osc1 rf (3) sleep t o inter nal logic rs (2) pic1 6c505 cloc k from e xt. system osc1 osc2 pic1 6c 5 05 open t ab le 7-1: c apacitor selection f or ceramic resonator s - pic1 6 c5 05 t ab le 7-2: c apacitor selection f or cr ystal oscillator - pic1 6 c5 05 osc t ype resonator freq cap. rang e c1 cap. rang e c2 xt 4.0 mhz 30 pf 30 pf hs 16 mhz 10-47 pf 10-47 pf these v alues are f or design guidance only . since each resonator has its o wn char acter istics , the user should consult the resonator man uf acturer f or appropr iate v alues of e xter nal components . osc t ype resonator freq cap.rang e c1 cap. rang e c2 lp 32 khz (1) 15 pf 15 pf xt 200 khz 1 mhz 4 mhz 47-68 pf 15 pf 15 pf 47-68 pf 15 pf 15 pf hs 20 mhz 15-47 pf 15-47 pf note 1: f or v dd > 4.5v , c1 = c2 ? 30 pf is recommended. these v alues are f or design guidance only . rs ma y be required in xt mode to a v oid o v erdr iving cr ystals with lo w dr iv e le v el speci cation. since each cr ystal has its o wn char acter istics , the user should consult the cr ystal man uf acturer f or appropr iate v alues of e xter nal components .
1998 microchip technology inc. preliminary ds40192a -page 29 pic16c505 7.2.3 e xter nal cr ystal oscillator circuit either a prepac kaged oscillator or a simple oscillator circuit with ttl gates can be used as an e xter nal cr ystal oscillator circuit. prepac kaged oscillators pro vide a wide oper ating r ange and better stability . a w ell-designed cr ystal oscillator will pro vide good perf or mance with ttl gates . t w o types of cr ystal oscillator circuits can be used: one with par allel resonance , or one with ser ies resonance . figure 7-4 sho ws implementation of a par allel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the cr ystal. the 74as04 in v er ter perf or ms the 180-deg ree phase shift that a par allel oscillator requires . the 4.7 k w resistor pro vides the negativ e f eedbac k f or stability . the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used f or e xter nal oscillator designs . figure 7-4: external p arallel resonant cr ystal oscillator cir cuit figure 7-5 sho ws a ser ies resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the cr ystal. the in v er ter perf or ms a 180- deg ree phase shift in a ser ies resonant oscillator circuit. the 330 w resistors pro vide the negativ e f eedbac k to bias the in v er ters in their linear region. figure 7-5: external series resonant cr ystal oscillator cir cuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xt al 10k 74as04 pic16c505 clkin t o other de vices 330 74as04 74as04 pic16c505 clkin t o other de vices xt al 330 74as04 0.1 m f 7.2.4 external rc oscillator f or timing insensitiv e applications , the rc de vice option off ers additional cost sa vings . the rc oscillator frequency is a function of the supply v oltage , the resistor (re xt) and capacitor (ce xt) v alues , and the oper ating temper ature . in addition to this , the oscillator frequency will v ar y from unit to unit due to nor mal process par ameter v ar iation. fur ther more , the diff erence in lead fr ame capacitance betw een pac kage types will also aff ect the oscillation frequency , especially f or lo w ce xt v alues . the user also needs to tak e into account v ar iation due to toler ance of e xter nal r and c components used. figure 7-6 sho ws ho w the r/c combination is connected to the pic16c505 . f or re xt v alues belo w 2.2 k w , the oscillator oper ation ma y become unstab le , or stop completely . f or v er y high re xt v alues (e .g., 1 m w ) the oscillator becomes sensitiv e to noise , humidity and leakage . thus , w e recommend k eeping re xt betw een 3 k w and 100 k w . although the oscillator will oper ate with no e xter nal capacitor (ce xt = 0 pf), w e recommend using v alues abo v e 20 pf f or noise and stability reasons . with no or small e xter nal capacitance , the oscillation frequency can v ar y dr amatically due to changes in e xter nal capacitances , such as pcb tr ace capacitance or pac kage lead fr ame capacitance . the electr ical speci cations sections sho w rc frequency v ar iation from par t to par t due to nor mal process v ar iation. the v ar iation is larger f or larger r (since leakage current v ar iation will aff ect rc frequency more f or large r) and f or smaller c (since v ar iation of input capacitance will aff ect rc frequency more). also , see the electr ical speci cations sections f or v ar iation of oscillator frequency due to v dd f or giv en re xt/ce xt v alues as w ell as frequency v ar iation due to oper ating temper ature f or giv en r, c , and v dd v alues . figure 7-6: external rc oscillator mode v dd re xt ce xt v ss osc1 inter nal cloc k pic16c505 n fosc/4 osc2/clk out
pic16c505 ds40192a -page 30 preliminary 1998 microchip technology inc. 7.2.5 inter nal 4 mh z rc oscillator the inter nal rc oscillator pro vides a x ed 4 mhz (nom- inal) system cloc k at vdd = 5v and 25 c , see ?lectr i- cal speci cations section f or inf or mation on v ar iation o v er v oltage and temper ature .. in addition, a calibr ation instr uction is p rog r ammed into the last address of memor y which contains t he calibr a- tion v alue f or t he inter nal rc oscillator . this location is alw a ys uncode protected regardless of the code pro- tect settings . this v alue is p rog r ammed as a movlw xx instr uction where xx is the calibr ation v alue , and is p laced at the reset v ector . this will load the w register with the calibr ation v alue upon reset and the pc will then roll o v er to the users prog r am at address 0 x000. the user then has the option of wr iting the v alue to the osccal register (05h) or ignor ing it. osccal, when wr itten to with the calibr ation v alue , will ?r im the inter nal oscillator to remo v e process v ar iation from the oscillator frequency . . f or the pic16c505, only bits <7:2> of osccal are implemented. 7.3 reset the de vice diff erentiates betw een v ar ious kinds of reset: a) p o w er on reset (por) b) mclr reset dur ing nor mal oper ation c) mclr reset dur ing sleep d) wdt time-out reset dur ing nor mal oper ation e) wdt time-out reset dur ing sleep f) w ak e-up from sleep on pin change some registers are not reset in an y w a y; the y are unkno wn on por and unchanged in an y other reset. most other registers are reset to ?eset state on po w er- on reset (por), on mclr , wdt or w ak e-up on pin change reset dur ing nor mal oper ation . the y are not aff ected b y a wdt reset dur ing sleep or mclr reset dur ing sleep , since these resets are vie w ed as resumption of nor mal oper ation. the e xceptions to this are t o , pd , and rbwuf bits . the y are set or cleared diff erently in diff erent reset situations . these bits are used in softw are to deter mine the nature of reset. see t ab le 7-3 f or a full descr iption of reset states of all registers . note: please note that er asing the de vice will also er ase the pre- prog r ammed inter nal calibr ation v alue f or the inter nal oscillator . the calibr ation v alue m ust be read p r ior to e r asing the par t. so it can be repro- g r ammed correctly later .
1998 microchip technology inc. preliminary ds40192a -page 31 pic16c505 t able 7-3: r eset conditions f or register s t able 7-4: r eset condition f or special register s register ad dress p o wer -on reset mclr reset wdt time-out w ake-up on pin chang e w qqqq xxxx (1) qqqq uuuu (1) indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pc 02h 1111 1111 1111 1111 st a tus 03h 0001 1xxx ?00? ?uuu (2) fsr 04h 110x xxxx 11uu uuuu osccal 05h 1000 00-- uuuu uu-- por tb 06h --xx xxxxx --uu uuuu por tc 07h --xx xxxxx --uu uuuu option 1111 1111 1111 1111 trisb --11 1111 --11 1111 trisc --11 1111 --11 1111 legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as ?? ? = v alue depends on condition. note 1: bits <7:4> of w register contain oscillator calibr ation v alues due to movlw xx instr uction at top of memor y . note 2: see t ab le 7-7 f or reset v alue f or speci c conditions st a tus ad dr: 03h pcl ad dr: 02h p o w er on reset 0001 1xxx 1111 1111 mclr reset dur ing nor mal oper ation 000u uuuu 1111 1111 mclr reset dur ing sleep 0001 0uuuu 1111 1111 wdt reset dur ing sleep 0000 0uuu 1111 1111 wdt reset nor mal oper ation 0000 1uuu 1111 1111 w ak e-up f rom sleep on pin change 1001 0uuu 1111 1111 legend: u = unchanged, x = unkno wn, - = unimplemented bit, read as ??
pic16c505 ds40192a -page 32 preliminary 1998 microchip technology inc. 7.3.1 mclr enable this con gur ation bit when unprog r ammed (left in the ? state) enab les the e xter nal mclr function. when prog r ammed, the mclr function is tied to the inter nal v dd , and the pin is assigned to be a i/o . see figure 7- 7 . figure 7-7: mclr select 7.4 p o wer -on reset ( por) the pic16c505 f amily incor por ates on-chip p o w er-on reset (por) circuitr y which pro vides an inter nal chip reset f or most po w er-up situations . a p o w er-on reset pulse is gener ated on-chip when v dd r ise is detected (in the r ange of 2.3 v - 2.8v). t o tak e adv antage of the inter nal por, prog r am the rb3/ mclr /v pp pin as mclr and tie directly to v dd or pro- g r am the pin as rb3. an inter nal w eak pull-up resistor is implemented using a tr ansistor . ref er to t ab le 10-6 f or the pull-up resistor r anges . this will eliminate e xter- nal rc components usually needed to create a p o w er- on reset. a maxim um r ise time f or v dd is speci ed. see electr ical speci cations f or details . when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper ating par ameters (v oltage , frequency , temper ature , ...) m ust be met to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating par ameters are met . a simpli ed b loc k diag r am of the on-chip p o w er-on reset circuit is sho wn in figure 7-8 . rb3/ mclr /v pp mclre internal mclr weak pull-up rbwu the p o w er-on reset circuit and the de vice reset timer ( section 7.5 ) circuit are closely related. on po w er-up , the reset latch is set and the dr t is reset. the dr t timer begins counting once it detects mclr to be high. after the time-out per iod, which is typically 18 ms , it will reset the reset latch and thus end the on- chip reset signal. a po w er-up e xample where mclr is held lo w is sho wn in figure 7-9 . v dd is allo w ed to r ise and stabiliz e bef ore br inging mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-10 , the on-chip p o w er-on reset f eature is being used ( mclr and v dd are tied together or the pin is prog r ammed to be rb3. ). the v dd is stab le bef ore the star t-up timer times out and there is no prob lem in getting a proper reset. ho w e v er , figure 7- 11 depicts a prob lem situation where v dd r ises too slo wly . the time betw een when the dr t senses that mclr is high and when m clr (and v dd ) actually reach their full v alue , is too long. in this situation, when the star t-up timer times out, v dd has not reached the v dd (min) v alue and the chip is , theref ore , not guar anteed to function correctly . f or such situations , w e recommend that e xter nal rc circuits be used to achie v e longer por dela y times ( figure 7-10 ). f or additional i nf or mation ref er to application notes p o w er-up consider ations - an522 and p o w er-up t roub le shooting - an607. note: when the de vice star ts nor mal oper ation (e xits the reset condition), de vice oper at- ing par ameters (v oltage , frequency , tem- per ature , etc.) m ust be meet to ensure oper ation. if these conditions are not met, the de vice m ust be held in reset until the oper ating conditions are met.
1998 microchip technology inc. preliminary ds40192a -page 33 pic16c505 figure 7-8: simplified bloc k dia gram of on-chip reset cir cuit figure 7-9: time-out sequence on p o wer -up ( mclr pulled lo w) figure 7-10: time-out sequence on p o wer -up ( mclr tied to v dd ): f ast v dd rise time s q r q v dd rb3/ m clr / v pp p o w er-up detect on-chip dr t osc por (p o w er-on reset) wdt time-out reset chip reset 8-bit asynch ripple counter (star t-up timer) mclre sleep pin change w ak e-up on pin change v dd mclr internal por dr t time-out internal reset t dr t v dd mclr internal por dr t time-out internal reset t dr t
pic16c505 ds40192a -page 34 preliminary 1998 microchip technology inc. figure 7-11: time-out sequence on p o wer -up ( mclr tied to v dd ): slo w v dd rise time v dd mclr internal por dr t time-out internal reset t dr t v 1 when v dd r ises slo wly , the t drt time-out e xpires long bef ore v dd has reached its nal v alue . in this e xample , the chip will reset proper ly if , and only if , v1 3 v dd min. 7.5 de vice reset timer (dr t) in the pic16c505, the dr t r uns an y time the de vice is po w ered up . dr t r uns from rese t and v ar ies based on oscillator selection (see t ab le 7-5 .) t he de vice reset timer (dr t) pro vides a x ed 18 ms nominal time-out on reset. the d r t o per ates on an inter nal rc oscillator . the processor is k ept in reset as long as the dr t is activ e . the dr t dela y allo ws v dd to r ise abo v e v dd min., and f or the oscillator to stabiliz e . oscillator circuits based on cr ystals or cer amic resonators require a cer tain time after po w er-up to estab lish a stab le oscillation. the on-chip dr t k eeps the de vice in a reset condition f or appro ximately 18 ms after mclr has reached a logic high (v ih mclr ) le v el. thus , prog r amming rb3/ mclr /v pp as mclr and using an e xter nal rc netw or k connected to the mclr input is not required in most cases , allo wing f or sa vings in cost-sensitiv e and/or space restr icted applications , as w ell as allo wing the use of the rb3/ mclr /v pp pin as a gener al pur pose input. the de vice reset time dela y will v ar y from chip to chip due to v dd , temper ature , and process v ar iation. see a c par ameters f or details . the dr t will also be tr iggered upon a w atchdog timer time-out (only in hs , xt and lp modes). this is par ticular ly impor tant f or applications using the wdt to w ak e from sleep mode automatically . 7.6 w atc hdog timer (wdt) the w atchdog timer (wdt) is a free r unning on-chip rc oscillator which does not require an y e xter nal components . this rc oscillator is separ ate from the e xter nal rc oscillator of the rb 5/ osc1/clkin pin and the inter nal 4 mhz oscillator . that means that the wdt will r un e v en if the main processor cloc k has been stopped, f or e xample , b y e x ecution of a sleep instr uction. dur ing nor mal oper ation or sleep , a wdt reset or w ak e-up r eset gener ates a de vice reset . the t o bit (st a tus<4>) will be cleared upon a w atchdog timer reset . the wdt can be per manently disab led b y prog r amming the con gur ation bit wdte as a '0' ( section 7.1 ). ref er to the pic16 c5 05 p rog r amming speci cations t o deter mine ho w to access the con gur ation w ord. t able 7-5: dr t (de vice reset timer p eriod) oscillator con guration por reset subsequent resets intrc & extrc 18 ms (typical) 300 m s (typi- cal) hs , xt & lp 18 ms (typical) 18 ms (typical)
1998 microchip technology inc. preliminary ds40192a -page 35 pic16c505 7.6.1 wdt p er iod the wdt has a nominal time-out per iod of 18 ms , (with no prescaler). i f a longer time-out per iod is d esired, a prescaler with a division r atio of up to 1:128 can be assigned to the wdt ( under softw are control ) b y wr iting to the option register . thus , a time-out per iod of a nominal 2 .3 seconds can be realiz ed. these per iods v ar y with temper ature , v dd and par t-to- par t process v ar iations (see dc specs). under w orst case conditions ( v dd = min., t emper ature = max., max. wdt prescaler), it ma y tak e se v er al seconds bef ore a wdt time-out occurs . 7.6.2 w dt prog r amming consider ations the clrwdt instr uction clears the wdt and the postscaler , if assigned to the wdt , and pre v ents it from timing out and gener ating a de vice reset . the sleep instr uction resets the wdt and the postscaler , if assigned to the wdt . this giv es the maxim um sleep time bef ore a wdt w ak e-up r eset. figure 7-12: w atc hdog timer bloc k dia gram t ab le 7-6: summar y of register s associated with the w atc hdog timer ad dress name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v alue o n p o wer -o n r eset v alue o n m clr an d w dt reset v alue on w ake-up on pin c hang e n/a option rbwu rbpu t0cs t0se psa ps2 ps1 ps0 1111 1 111 1111 1 111 1111 1111 legend: shaded bo x es = not used b y w atchdog timer , = unimplemented, read as '0', u = unchanged 1 0 1 0 f rom t imer0 cloc k sourc e ( figure 6-5 ) t o timer0 ( figure 6-4 ) p ostscaler wdt enab le con gur ation bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux p ostscaler m u x w atchdog timer note: t0cs , t0se, psa, ps2:ps0 are bits in the option register .
pic16c505 ds40192a -page 36 preliminary 1998 microchip technology inc. 7.7 time-out sequence , p o wer do wn , and w ake-up fr om sleep s tatus bits ( t o / pd / rb wu f ) the t o , p d , and rbwuf b its in the st a tus register can be tested to deter mine if a reset condition has been caused b y a po w er-up condition, a mclr or w atchdog timer (wdt) reset, or a mclr or wdt re set. these st a tus bits are only aff ected b y e v ents listed in t ab le 7-8 . t ab le 7-4 lists the reset conditions f or the special function registers , while t ab le 7-3 lists the reset conditions f or all the registers . t ab le 7-7: t o / pd /rbwuf status after rese t rb wuf t o pd reset c aused b y 0 0 0 wdt w ak e-up from sleep 0 0 1 wdt time-out (not fro m s leep) 0 1 0 mclr w ak e-up f ro m s leep 0 1 1 p o w er-up 0 u u mclr not dur ing sleep 1 1 0 w ak e-up from sleep on pin change legend: legend: u = unchanged note 1: the t o , p d , and rb wuf b its main- tain their status ( u ) until a reset occurs . a lo w-pulse on the mclr input does not change the t o , pd , and rb wuf s tatus bits . t ab le 7-8: events aff ecting t o / pd status bits event rb wuf t o pd remarks p o w er-up 0 1 1 wdt time - out 0 0 u no eff ec t o n pd sleep instr uction u 1 0 clr wd t i nstr uction u 1 1 w ak e-up from sleep on pin change 1 1 0 legend: u = unchanged a wdt time-out will occur regardless of the status of the t o bit. a sleep instr uction will be e x ecuted, regardless of the status of the pd bit. t ab le 7-7 re ects the status of t o and pd after the corresponding e v ent. 7.8 reset on br o wn-out a bro wn-out is a condition where de vice po w er (v dd ) dips belo w its minim um v alue , b ut not to z ero , and then reco v ers . the de vice should be reset in the e v ent of a bro wn-out. t o reset pic1 6 c5 05 de vices when a bro wn-out occurs , e xter nal bro wn-out protection circuits ma y be b uilt, as sho wn in figure 7-13 and figure 7-14 . figure 7-13: br o wn-out pr otection cir cuit 1 figure 7-14: br o wn-out pr otection cir cuit 2 this circuit will activ ate reset when v dd goes belo w vz + 0.7v (w here vz = zener v oltage ) . *ref er to figure 7-7 and t ab le 10-6 f or inter nal w eak pull- up on mclr. 33k 10k 40k* v dd mclr pic 1 6 c5 05 v dd q1 t his bro wn-out circuit is less e xpensiv e , although less accur ate . t r ansistor q1 tur ns off when v dd is belo w a cer tain le v el such that: *ref er to figure 7-7 and t ab le 10-6 f or inter nal w eak pull-up on mclr. v dd r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16 c 505 r1 q1 v dd
1998 microchip technology inc. preliminary ds40192a -page 37 pic16c505 7.9 p o wer -do wn mode (sleep) a de vice ma y be po w ered do wn (sleep) and later po w ered up (w ak e-up from sleep). 7.9.1 sleep the p o w er-do wn mode is entered b y e x ecuting a sleep instr uction. if enab led, the w atchdog timer will be cleared b ut k eeps r unning, the t o bit (st a tus<4>) is set, the pd bit (st a tus<3>) is cleared and the oscillator dr iv er is tur ned off . the i/o por ts maintain the status the y had bef ore the sleep instr uction w as e x ecuted (dr iving high, dr iving lo w , or hi-impedance). it should be noted that a reset gener ated b y a wdt time-out does not dr iv e the mclr pin lo w . f or lo w est current consumption while po w ered do wn, the t0cki input should be at v dd or v ss and the rb 3/ mclr /v pp pin m ust be at a logic high le v el ( v ihmc ) if mclr is e nab le d . 7.9.2 w ak e-up from sleep the de vice can w ak e-up from sleep through one of the f ollo wing e v ents: 1. an e xter nal reset input on rb 3/ mclr / v pp pin , when con gured as mclr . 2. a w atchdog timer time-out reset (if wdt w as enab led). 3. a change on input pin rb 0, rb 1, rb 3 or rb4 when w ak e-up on change is enab led. t hese e v ents cause a d e vice reset. the t o , p d , and rb wuf b its can be used to deter mine the cause of de vice reset. t he t o bit is cleared if a wdt time-out occurred (and caused w ak e-up). the pd bit, which is set on po w er-up , is cleared when sleep is in v ok ed. the rb wuf bit indicates a change in state while in sleep at pins rb 0, rb 1, rb 3 or rb4 ( since the last le or bit oper ation on rb por t). the wdt is cleared when the de vice w ak es from sleep , regardless of the w ak e-up source . caution: right bef ore enter ing sleep , read the input pins . when in sleep , w ak e up occurs when the v alues at the pins change from the state the y w ere in at the last reading. if a w ak e - up on change occurs and the pins are not read bef ore reenter ing sleep , a w ak e up will occur immediately e v en if no pins change while in sleep mode . 7.10 p r ogram v eri cation/code pr otection if the code protection bit ha s not been prog r ammed, the on-chip prog r am memor y can be read out f or v er i cation pur poses . the rst 64 locations and the last location (osccal) can be read regardless of the code protection bit setting. 7.11 id locations f our memor y locations are designated as id locations where the user can store chec ksum or other code- identi cation n umbers . these locations are not accessib le dur ing nor mal e x ecution b ut are readab le and wr itab le dur ing prog r am/v er ify . use only the lo w er 4 bits of the id locations and alw a ys prog r am the upper 8 bits as ' 0' s .
pic16c505 ds40192a -page 38 preliminary 1998 microchip technology inc. 7.12 i n-cir cuit serial pr ogramming the pic1 6 c5 05 microcontrollers can be ser ially prog r ammed while in the end application circuit. this is simply done with tw o lines f or cloc k and data, and three other lines f or po w er , g round, and the prog r amming v oltage . this allo ws customers to man uf acture boards with unprog r ammed de vices , and then prog r am the microcontroller just bef ore shipping the product. this also allo ws the most recent r mw are or a custom r mw are to be prog r ammed. the de vice is placed into a prog r am/v er ify mode b y holding the rb 1 a nd rb 0 p ins lo w while r aising the mclr ( v pp ) pin from v il to v ihh ( see prog r amming speci cation). rb 1 b ecomes the prog r amming cloc k and rb 0 b ecomes the prog r amming data. both rb 1 a nd rb 0 a re schmitt t r igger inputs in this mode . after reset, a 6-bit command is then supplied to the de vice . depending on the command, 14-bits of pro- g r am data are then supplied to or from the de vice , depending if the command w as a load or a read. f or complete details of ser ial prog r amming, please ref er to the pic1 6 c5 05 p rog r amming speci cations . a typical in-circuit ser ial prog r amming connection is sho wn in figure 7-15 . figure 7-15: t ypical in-cir cuit serial pr ogramming connection exter nal connector signals t o nor mal connections t o nor mal connections pic16c 5 05 v dd v ss mclr / v pp rb 1 rb 0 +5v 0v v pp clk data i/o v dd
1998 microchip technology inc. preliminary ds40192a -page 39 pic16c505 8.0 instruction set summar y each pic16c505 instr uction is a 12-bit w ord divided into an opcode, which speci es the instr uction type , and one or more oper ands which fur ther specify the oper ation of the instr uction. the pic16c505 instr uction set summar y in t ab le 8-2 g roups the instr uctions into b yte-or iented, bit-or iented, and liter al and control oper ations . t ab le 8-1 sho ws the opcode eld descr iptions . f or b yte-oriented instr uctions , 'f' represents a le register designator and 'd' represents a destination designator . the le register designator is used to specif y w hich one of the 32 f ile registers is to be used b y the instr uction. the destination designator speci es where the result of the oper ation is to be placed. if 'd' is '0', the result is placed in the w register . if 'd' is '1', the result is placed in the le register speci ed in the instr uction. f or bit-oriented instr uctions , 'b' represents a bit eld designator which selects the n umber of the bit aff ected b y the oper ation, while 'f' represents the n umber of the le in which the bit is located. f or literal and contr ol oper ations , 'k' represents an 8 o r 9-bit constant or liter al v alue . t ab le 8-1: opcode field descriptions field description f register le address (0x00 to 0x7f) w w or king register (accum ulator) b bit address within an 8-bit le register k liter al eld, constant data or label x don't care location (= 0 or 1) the assemb ler will gener ate code with x = 0. it is the recommended f or m of use f or compatibility with all microchip softw are tools . d destination select; d = 0 (store result in w) d = 1 (store result in le register 'f' ) d ef ault is d = 1 label label name tos t op of stac k pc prog r am counter wdt w atchdog timer counter to time-out bit pd p o w er-do wn bit dest destination, either the w register or the speci ed register le location [ ] options ( ) contents ? assigned to < > register bit eld ? in the set of i talics user de ned ter m (f ont is cour ier) all instr uctions are e x ecuted within a s ingle instr uction cycle , unless a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction. in this case , the e x ecution tak es tw o instr uction cycles . one instr uction cycle consists of f our oscillator per iods . thus , f or an oscillator frequency of 4 mhz, the nor mal instr uction e x ecution time is 1 m s . if a conditional test is tr ue or the prog r am counter is changed as a result of an instr uction, the instr uction e x ecution time is 2 m s . figure 8-1 sho ws the three gener al f or mats that the instr uctions can ha v e . a ll e xamples in the gure use the f ollo wing f or mat to represent a he xadecimal n umber : 0xhh h where ' h ' signi es a he xadecimal digit. figure 8-1: g eneral format f or instructions byte-oriented le register oper ations 1 1 6 5 4 0 d = 0 f or destination w opcode d f (file #) d = 1 f or destination f f = 5- bit le register address bit-oriented le register oper ations 1 1 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5- bit le register address literal and contr ol oper ations (e xcept goto ) 1 1 8 7 0 opcode k ( liter al) k = 8-bit immediate v alue literal and contr ol oper ations - goto instr uction 1 1 9 8 0 opcode k ( liter al) k = 9- bit immediate v alue
pic16c505 ds40192a -page 40 preliminary 1998 microchip technology inc. t ab le 8-2: instruction set summar y mnemonic, operands description cyc les 12-bit opcode status aff ected notes msb lsb add wf and wf clrf clr w comf decf decfsz incf incfsz ior wf mo vf mo vwf nop rlf rrf subwf sw apf xor wf f ,d f ,d f f , d f , d f , d f , d f , d f , d f , d f f , d f , d f , d f , d f , d add w and f and w with f clear f clear w complement f decrement f decrement f , skip if 0 increment f increment f , skip if 0 inclusiv e or w with f mo v e f mo v e w to f no oper ation rotate left f through carr y rotate r ight f through carr y subtr act w from f sw ap f exclusiv e or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c ,dc ,z z z z z z none z none z z none none c c c ,dc ,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit -oriented file register opera tions bcf bsf btfsc btfss f , b f , b f , b f , b bit clear f bit set f bit t est f , skip if clear bit t est f , skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and contr ol opera tions andl w call clr wdt go t o iorl w mo vl w option retl w sleep tris xorl w k k k k k k k f k and liter al with w call subroutine clear w a tchdog ti mer unconditional br anch inclusiv e or li ter al with w mo v e liter al to w load option register retur n, place li ter al in w go into standb y mode load tris register exclusiv e or liter al to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none t o , pd none z none none none t o , pd none z 1 3 note 1: the 9th bit of the prog r am counter will be f orced to a '0' b y an y instr uction that wr ites to the pc e xcept f or goto . ( section 4.6 ) 2: when an i/o register is modi ed as a function of itself (e .g. movf portb, 1 ), the v alue used will be that v alue present on the pins themselv es . f or e xample , if the data latch is '1' f or a pin con gured as input and is dr iv en lo w b y an e xter nal de vice , the data will be wr itten bac k with a '0'. 3: the instr uction tris f , where f = 6 causes the contents of the w register to be wr itten to the tr istate latches of por tb . a '1' f orces the pin to a hi-impedance state and disab les the output b uff ers . 4: if this instr uction is e x ecuted on the tmr0 register (and, where applicab le , d = 1), the prescaler will be cleared (if assigned to tmr0).
1998 microchip technology inc. preliminary ds40192a -page 41 pic16c505 add wf ad d w and f syntax: [ label ] add wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) + (f) ? (dest) status aff ected: c , dc , z encoding: 0001 11df ffff descr iption: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is ' 1 ' the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example: addwf fsr , 0 b ef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0xd9 fsr = 0xc2 andl w and li teral with w syntax: [ label ] andl w k oper ands: 0 k 255 oper ation: (w) . and . (k) ? (w) status aff ected: z encoding: 1110 kkkk kkkk descr iption: the contents of the w register are and?d with the eight-bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: andlw 0x5f b ef ore instr uction w = 0xa3 after instr uction w = 0x03 and wf and w with f syntax: [ label ] and wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) .and . (f) ? (dest) status aff ected: z encoding: 0001 01df ffff descr iption: the contents of the w register are and?d with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is ' 1 ' the result is stored bac k in register 'f' . w ords: 1 cycles: 1 example: andwf fsr, 1 b ef ore instr uction w = 0x17 fsr = 0xc2 after instr uction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f ,b oper ands: 0 f 31 0 b 7 oper ation: 0 ? ( f < b> ) status aff ected: none encoding: 0100 bbbf ffff descr iption: bit 'b' in register 'f' is cleared. w ords: 1 cycles: 1 example: bcf flag_reg, 7 b ef ore instr uction fla g_reg = 0xc7 after instr uction fla g_reg = 0x47
pic16c505 ds40192a -page 42 preliminary 1998 microchip technology inc. bsf bit set f syntax: [ label ] bsf f ,b oper ands: 0 f 31 0 b 7 oper ation: 1 ? ( f ) status aff ected: none encoding: 0101 bbbf ffff descr iption: bit 'b' in register 'f' is set. w ords: 1 cycles: 1 example: bsf flag_reg, 7 b ef ore instr uction fla g_reg = 0x0a after instr uction fla g_reg = 0x8a btfsc b it t est f , sk ip if clear syntax: [ label ] btfsc f ,b oper ands: 0 f 31 0 b 7 oper ation: skip if (f) = 0 status aff ected: none encoding: 0110 bbbf ffff descr iption: if bit 'b' in register 'f' is 0 t hen the ne xt instr uction is skipped. if bit 'b' is 0 t hen the ne xt instr uction f etched dur ing the current instr uction e x ecution is discarded, and a n nop is e x ecuted instead, making this a 2 cycle instr uction. w ords: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code b ef ore instr uction pc = address (here) after instr uction if fla g<1> = 0, pc = address (true) ; if fla g<1> = 1, pc = a ddress (false) btfss bit t est f , sk ip if set syntax: [ label ] btfss f ,b oper ands: 0 f 31 0 b < 7 oper ation: skip if (f) = 1 status aff ected: none encoding: 0111 bbbf ffff descr iption: if bit 'b' in register 'f' is '1' then the ne xt instr uction is skipped. if bit 'b' is '1', then the ne xt instr uction f etched dur ing the current instr uction e x ecution, is discarded and a n nop is e x ecuted instead, making this a 2 cycle instr uction. w ords: 1 cycles: 1 (2) example: here btfss flag,1 false goto process_code true bef ore instr uction pc = address (here) after instr uction if fla g<1> = 0, pc = address (false) ; if fla g<1> = 1, pc = address (true)
1998 microchip technology inc. preliminary ds40192a -page 43 pic16c505 call subr outine call syntax: [ label ] call k oper ands: 0 k 2 55 oper ation: (pc) + 1 ? t op of stac k; k ? pc< 7: 0> ; ( st a tus<6:5>) ? pc<10:9> ; 0 ? pc<8> status aff ected: none encoding: 1001 kkkk kkkk descr iption: subroutine call. first, retur n address (pc+1) is pushed onto the stac k. the eight bit immediate address is loaded into pc bits < 7 :0>. the upper bits pc <10:9> a re loaded from st a- tus<6:5>, pc<8> is cleared. call is a tw o cycle instr uction. w ords: 1 cycles: 2 example: here call there b ef ore instr uction pc = ad dress (here) after instr uction pc = ad dress (there) t os = ad dress (here + 1 ) clrf clear f syntax: [ label ] clrf f oper ands: 0 f 31 oper ation: 00h ? ( f ); 1 ? z status aff ected: z encoding: 0000 011f ffff descr iption: the contents of register 'f' are cleared and the z bit is set. w ords: 1 cycles: 1 example: clrf flag_reg b ef ore instr uction fla g_reg = 0x5a after instr uction fla g_reg = 0x00 z = 1 clr w clear w syntax: [ label ] clr w oper ands: none oper ation: 00h ? (w) ; 1 ? z status aff ected: z encoding: 0000 0100 0000 descr iption: the w register i s cleared. zero bit (z) is set. w ords: 1 cycles: 1 example: clrw b ef ore instr uction w = 0x5a after instr uction w = 0x00 z = 1 clr wdt clear w atc hdog timer syntax: [ label ] clr wdt oper ands: none oper ation: 00h ? wdt ; 0 ? wdt prescaler (if assigned) ; 1 ? t o; 1 ? pd status aff ected: t o , pd encoding: 0000 0000 0100 descr iption: the clrwdt i nstr uction resets the wdt . it also resets the prescaler , if the prescaler is assigned to the wdt and not timer0. status bits t o and pd are set. w ords: 1 cycles: 1 example: clrwdt b ef ore instr uction wdt counter = ? after instr uction wdt counter = 0x00 wdt prescale = 0 t o = 1 pd = 1
pic16c505 ds40192a -page 44 preliminary 1998 microchip technology inc. comf complement f syntax: [ label ] comf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f ) ? (dest) status aff ected: z encoding: 0010 01df ffff descr iption: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: comf reg1,0 b ef ore instr uction reg1 = 0x13 after instr uction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ?1 ? (dest) status aff ected: z encoding: 0000 11df ffff descr iption: decrement register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: decf cnt, 1 b ef ore instr uction cnt = 0x01 z = 0 after instr uction cnt = 0x00 z = 1 decfsz decrement f , sk ip if 0 syntax: [ label ] decfsz f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ?1 ? d; s kip if result = 0 status aff ected: none encoding: 0010 11df ffff descr iption: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, the ne xt instr uction, which is already f etched, is discarded and an n op is e x ecuted instead mak- ing it a tw o cycle instr uction. w ords: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue b ef ore instr uction pc = address (here) after instr uction cnt = cnt - 1; if cnt = 0, pc = addres s (continue) ; if cnt 1 0, pc = addres s (here+1) go t o unconditional branc h syntax: [ label ] go t o k oper ands: 0 k 511 oper ation: k ? pc<8:0>; st a tus<6:5> ? pc<10:9> status aff ected: none encoding: 101k kkkk kkkk descr iption: goto is an unconditional br anch. the 9-b it immediate v alue is loaded into pc bits < 8 :0>. the upper bits of pc are loaded from st a tus < 6 : 5 >. goto is a tw o cycle instr uction. w ords: 1 cycles: 2 example: goto there a fter instr uction pc = address (there)
1998 microchip technology inc. preliminary ds40192a -page 45 pic16c505 incf increment f syntax: [ label ] incf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) + 1 ? (dest) status aff ected: z encoding: 0010 10df ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: incf cnt, 1 b ef ore instr uction cnt = 0xff z = 0 after instr uction cnt = 0x00 z = 1 incfsz increment f , sk ip if 0 syntax: [ label ] incfsz f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) + 1 ? (dest), skip if result = 0 status aff ected: none encoding: 0011 11df ffff descr iption: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. if the result is 0, then the ne xt instr uc- tion, which is already f etched, is dis- carded and an n op is e x ecuted instead making it a tw o cycle instr uc- tion. w ords: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue b ef ore instr uction pc = address (here) after instr uction cnt = cnt + 1; if cnt = 0 , pc = addres s (continue) ; if cnt 1 0 , pc = addres s (here +1) iorl w inc lusive or li teral with w syntax: [ label ] iorl w k oper ands: 0 k 255 oper ation: (w) .or. (k) ? (w) status aff ected: z encoding: 1101 kkkk kkkk descr iption: the contents of the w register are or?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: iorlw 0x35 b ef ore instr uction w = 0x9a after instr uction w = 0xbf z = 0 ior wf inc lusive or w with f syntax: [ label ] ior wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) . or. (f) ? (dest) status aff ected: z encoding: 0001 00df ffff descr iption: inclusiv e or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: iorwf result, 0 b ef ore instr uction resul t = 0x13 w = 0x91 after instr uction resul t = 0x13 w = 0x93 z = 0
pic16c505 ds40192a -page 46 preliminary 1998 microchip technology inc. mo vf mo ve f syntax: [ label ] mo vf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (f) ? (dest) status aff ected: z encoding: 0010 00df ffff descr iption: the contents of register ' f ' is mo v ed to destination ' d ' . if ' d ' is 0 , destination is the w register . if ' d ' is 1 , the destination is le register ' f '. ' d ' is 1 is useful to test a le register since status ag z is aff ected. w ords: 1 cycles: 1 example: movf fsr, 0 a fter instr uction w = v alue in fsr register mo vl w mo ve literal to w syntax: [ label ] mo vl w k oper ands: 0 k 255 oper ation: k ? (w) status aff ected: none encoding: 1100 kkkk kkkk descr iption: the eight bit liter al 'k' is loaded into the w register . the don? cares will assem- b le as 0s . w ords: 1 cycles: 1 example: movlw 0x5a a fter instr uction w = 0x5a mo vwf mo ve w to f syntax: [ label ] mo vwf f oper ands: 0 f 31 oper ation: (w) ? (f) status aff ected: none encoding: 0000 001f ffff descr iption: mo v e data from the w register to regis- ter 'f' . w ords: 1 cycles: 1 example: movwf temp_reg b ef ore instr uction temp_reg = 0xff w = 0x4f after instr uction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop oper ands: none oper ation: no oper ation status aff ected: none encoding: 0000 0000 0000 descr iption: no oper ation. w ords: 1 cycles: 1 example: nop
1998 microchip technology inc. preliminary ds40192a -page 47 pic16c505 option load option register syntax: [ label ] option oper ands: none oper ation: ( w ) ? option status aff ected: none encoding: 0000 0000 0010 descr iption: the content of the w register is loaded into the option register . w ords: 1 cycles: 1 example option b ef ore instr uction w = 0x07 after instr uction option = 0x0 7 retl w return with li teral in w syntax: [ label ] retl w k oper ands: 0 k 255 oper ation: k ? ( w ); t os ? pc status aff ected: none encoding: 1000 kkkk kkkk descr iption: the w register is loaded with the eight bit liter al 'k'. the prog r am counter is loaded from the top of the stac k (the retur n address). this is a tw o cycle instr uction. w ords: 1 cycles: 2 example : table call table ; w contains ; t able offset ;v alue . ? ;w now has table ? ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table b ef ore instr uction w = 0x07 after instr uction w = v alue of k 8 rlf rotate left f thr ough carr y syntax: [ label ] rlf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 0011 01df ffff descr iption: the contents of register 'f' are rotated one bit to the left through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example: rlf reg1,0 b ef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 1100 1100 c = 1 rrf rotate right f thr ough carr y syntax: [ label ] rrf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: see descr iption belo w status aff ected: c encoding: 0011 00df ffff descr iption: the contents of register 'f' are rotated one bit to the r ight through the carr y flag. if 'd' is 0 the result is placed in the w register . if 'd' is 1 the result is placed bac k in register 'f'. w ords: 1 cycles: 1 example: rrf reg1,0 b ef ore instr uction reg1 = 1110 0110 c = 0 after instr uction reg1 = 1110 0110 w = 0111 0011 c = 0 c register ' f ' c register ' f '
pic16c505 ds40192a -page 48 preliminary 1998 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep oper ands: none oper ation: 00h ? wdt ; 0 ? wdt prescaler ; 1 ? t o ; 0 ? pd status aff ected: t o , pd , rb wuf encoding: 0000 0000 0011 descr iption: time-out status bit ( t o ) is set. the po w er do wn status bit ( pd ) is cleared. rb wuf is unaff ected. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep f or more details . w ords: 1 cycles: 1 example: sleep subwf subtract w fr om f syntax: [ label ] subwf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f ) ?( w) ? ( dest) status aff ected: c , dc , z encoding: 0000 10df ffff descr iption: subtr act (2 s complement method ) the w register from register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example 1 : subwf reg1, 1 bef ore instr uction reg1 = 3 w = 2 c = ? after instr uction reg1 = 1 w = 2 c = 1 ; result is positiv e e xample 2 : bef ore instr uction reg1 = 2 w = 2 c = ? after instr uction reg1 = 0 w = 2 c = 1 ; result is z ero e xample 3 : bef ore instr uction reg1 = 1 w = 2 c = ? after instr uction reg1 = ff w = 2 c = 0 ; result is negativ e
1998 microchip technology inc. preliminary ds40192a -page 49 pic16c505 sw apf swap nibb les in f syntax: [ label ] sw apf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: ( f< 3:0>) ? ( d est < 7:4>); ( f< 7:4>) ? ( d est < 3:0>) status aff ected: none encoding: 0011 10df ffff descr iption: the upper and lo w er nib b les of register 'f' are e xchanged. if 'd' is 0 the result is placed in w register . if 'd' is 1 the result is placed in register 'f'. w ords: 1 cycles: 1 example swapf reg1, 0 bef ore instr uction reg 1 = 0x a5 after instr uction reg 1 = 0x a5 w = 0x5a tris load tris register syntax: [ label ] tris f oper ands: f = 6 oper ation: ( w ) ? tris register f status aff ected: none encoding: 0000 0000 0fff descr iption: tris register 'f' (f = 6 or 7) is loaded with the contents of the w register w ords: 1 cycles: 1 example tris portb bef ore instr uction w = 0xa5 after instr uction tris = 0xa5 xorl w exc lusive or li teral with w syntax: [ label ] xorl w k oper ands: 0 k 255 oper ation: (w) .xor. k ? ( w) status aff ected: z encoding: 1111 kkkk kkkk descr iption: the contents of the w register are xor?d with the eight bit liter al 'k'. the result is placed in the w register . w ords: 1 cycles: 1 example: xorlw 0xaf b ef ore instr uction w = 0xb5 after instr uction w = 0x1a xor wf exc lusive or w with f syntax: [ label ] xor wf f ,d oper ands: 0 f 31 d ? [0,1] oper ation: (w) .xor. (f) ? ( dest) status aff ected: z encoding: 0001 10df ffff descr iption: exclusiv e or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register . if 'd' is 1 the result is stored bac k in register 'f'. w ords: 1 cycles: 1 example xorwf reg ,1 b ef ore instr uction reg = 0xaf w = 0xb5 after instr uction reg = 0x1a w = 0xb5
pic16c505 ds40192a -page 50 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40192a -page 51 pic16c505 9.0 de velopment suppor t 9.1 de velopme nt t ools the picmicr o? microcontrollers are suppor ted with a full r ange of hardw are and softw are de v elopment tools: picmaster a /picmaster ce real-time in-circuit em ulator icepic ? lo w-cost pic16c5x and pic16cxxx in-circuit em ulator pr o ma te a ii univ ersal prog r ammer picst ar t a plus entr y-le v el prototype prog r ammer picdem-1 lo w-cost demonstr ation board picdem-2 lo w-cost demonstr ation board picdem-3 lo w-cost demonstr ation board mp asm assemb ler mplab ? sim softw are sim ulator mplab-c17 (c compiler) fuzzy logic de v elopment system ( fuzzy tech a - mp) 9.2 picmaster: high p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster univ ersal in-circuit em ulator is intended to pro vide the product de v elopment engineer with a complete microcontroller design tool set f or all microcontrollers in the pic14c000, pic12cxxx, pic16c5x, pic16cxxx and pic17cxx f amilies . picmaster is supplied with the mplab ? integ r ated de v elopment en vironment (ide), which allo ws editing, ?ak e and do wnload, and source deb ugging from a single en vironment. interchangeab le target probes allo w the system to be easily recon gured f or em ulation of diff erent proces- sors . the univ ersal architecture of the picmaster allo ws e xpansion to suppor t all ne w microchip micro- controllers . the picmaster em ulator system has been designed as a real-time em ulation system with adv anced f eatures that are gener ally f ound on more e xpensiv e de v elopment tools . the pc compatib le 386 (and higher) machine platf or m and microsoft win do ws a 3.x en vironment w ere chosen to best mak e these f ea- tures a v ailab le to y ou, the end user . a ce compliant v ersion of picmaster is a v ailab le f or european union (eu) countr ies . 9.3 icepic: lo w-cost picmicr o in-cir cuit em ulator icepic is a lo w-cost in-circuit em ulator solution f or the microchip pic12cxxx, pic16c5x and pic16cxxx f amilies of 8-bit o tp microcontrollers . icepic is designed to oper ate on pc-compatib le machines r anging from 286-a t a through p entium ? based machines under windo ws 3.x en vironment. icepic f eatures real time , non-intr usiv e em ulation. 9.4 pr o ma te ii: univer sal pr ogrammer the pr o ma te ii univ ersal prog r ammer is a full-f ea- tured prog r ammer capab le of oper ating in stand-alone mode as w ell as pc-hosted mode . pr o ma te ii is ce compliant. the pr o ma te ii has prog r ammab le v dd and v pp supplies which allo ws it to v er ify prog r ammed memor y at v dd min and v dd max f or maxim um reliability . it has an lcd displa y f or displa ying error messages , k e ys to enter commands and a modular detachab le soc k et assemb ly to suppor t v ar ious pac kage types . in stand- alone mode the pr o ma te ii can read, v er ify or pro- g r am pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices . it can also set con gur ation and code-protect bits in this mode . 9.5 picst ar t plus entr y le vel de velopment system the picst ar t prog r ammer is an easy-to-use , lo w- cost prototype prog r ammer . it connects to the pc via one of the com (rs-232) por ts . mplab integ r ated de v elopment en vironment softw are mak es using the prog r ammer simple and ef cient. picst ar t plus is not recommended f or production prog r amming. picst ar t plus suppor ts all pic12cxxx, pic14c000, pic16c5x, pic16cxxx and pic17cxx de vices with up to 40 pins . larger pin count de vices such as the pic16c923, pic16c924 and pic17c756 ma y be sup- por ted with an adapter soc k et. picst ar t plus is ce compliant.
pic16c505 ds40192a -page 52 preliminary 1998 microchip technology inc. 9.6 picdem-1 lo w-cost picmicr o demonstration boar d the picdem-1 is a simple board which demonstr ates the capabilities of se v er al of microchip s microcontrol- lers . the microcontrollers suppor ted are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessar y hardw are and softw are is included to r un basic demo prog r ams . the users can prog r am the sample micro controllers pro vided with the picdem-1 board, on a pr o ma te ii or picst ar t -plus prog r ammer , and easily test r m- w are . the user can also connect the picdem-1 board to the picmaster em ulator and do wn load the r mw are to the em ulator f or testing. additional pro- totype area is a v ailab le f or the user to b uild some addi- tional hardw are and connect it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , a potentiometer f or sim ulated analog input, push-b utton s witches and eight leds connected to por tb . 9.7 picdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstr ation board that suppor ts the pic16c62, pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers . all the necessar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can prog r am the sample microcontrollers pro vided with the picdem-2 board, on a pr o ma te ii pro- g r ammer or picst ar t -plus , and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-2 board to test r mw are . additional prototype area has been pro vided to the user f or adding addi- tional hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include a rs-232 inter- f ace , push-b utton s witches , a potentiometer f or sim u- lated analog input, a ser ial eepr om to demonstr ate usage of the i 2 c b us and separ ate headers f or connec- tion to an lcd module and a k e ypad. 9.8 picdem-3 lo w-cost pic16cxxx demonstration boar d the picdem-3 is a simple demonstr ation board that suppor ts the pic16c923 and pic16c924 in the plcc pac kage . it will also suppor t future 44-pin plcc microcontrollers with a lcd module . all the neces- sar y hardw are and softw are is included to r un the basic demonstr ation prog r ams . the user can pro- g r am the sample microcontrollers pro vided with the picdem-3 board, on a pr o ma te ii prog r am- mer or picst ar t plus with an adapter soc k et, and easily test r mw are . the picmaster em ulator ma y also be used with the picdem-3 board to test r m- w are . additional prototype area has been pro vided to the user f or adding hardw are and connecting it to the microcontroller soc k et(s). some of the f eatures include an rs-232 interf ace , push-b utton s witches , a potenti- ometer f or sim ulated analog input, a ther mistor and separ ate headers f or connection to an e xter nal lcd module and a k e ypad. also pro vided on the picdem-3 board is an lcd panel, with 4 commons and 12 seg- ments , that is capab le of displa ying time , temper ature and da y of the w eek. the picdem-3 pro vides an addi- tional rs-232 interf ace and windo ws 3.1 softw are f or sho wing the dem ultiple x ed lcd signals on a pc . a sim- ple ser ial interf ace allo ws the user to constr uct a hard- w are dem ultiple x er f or the lcd signals . 9.9 mplab integrated de velopment en vir onment software the mplab ide softw are br ings an ease of softw are de v elopment pre viously unseen in the 8-bit microcon- troller mar k et. mplab is a windo ws based application which contains: a full f eatured editor three oper ating modes - editor - em ulator - sim ulator a project manager customizab le tool bar and k e y mapping a status bar with project inf or mation extensiv e on-line help mplab allo ws y ou to: edit y our source les (either assemb ly or ?? one touch assemb le (or compile) and do wnload to picmicro tools (automatically updates all project inf or mation) deb ug using: - source les - absolute listing le t r ansf er data dynamically via dde (soon to be replaced b y ole) run up to f our em ulators on the same pc the ability to use mplab with microchip s sim ulator allo ws a consistent platf or m and the ability to easily s witch from the lo w cost sim ulator to the full f eatured em ulator with minimal retr aining due to de v elopment tools . 9.10 assemb ler (mp asm) the mp asm univ ersal macro assemb ler is a pc- hosted symbolic assemb ler . it suppor ts all microcon- troller ser ies including the pic12c5xx, pic14000, pic16c5x, pic16cxxx, and pic17cxx f amilies . mp asm off ers full f eatured macro capabilities , condi- tional assemb ly , and se v er al source and listing f or mats . it gener ates v ar ious object code f or mats to suppor t microchip's de v elopment tools as w ell as third par ty prog r ammers . mp asm allo ws full symbolic deb ugging from picmaster, microchip s univ ersal em ulator system.
1998 microchip technology inc. preliminary ds40192a -page 53 pic16c505 mp asm has the f ollo wing f eatures to assist in de v elop- ing softw are f or speci c use applications . pro vides tr anslation of assemb ler source code to object code f or all microchip microcontrollers . macro assemb ly capability . produces all the les (object, listing, symbol, and special) required f or symbolic deb ug with microchip s em ulator systems . suppor ts he x (def ault), decimal and octal source and listing f or mats . mp asm pro vides a r ich directiv e language to suppor t prog r amming of the picmicro . directiv es are helpful in making the de v elopment of y our assemb le source code shor ter and more maintainab le . 9.11 software sim ulator (mplab-sim) the mplab-sim softw are sim ulator allo ws code de v elopment in a pc host en vironment. it allo ws the user to sim ulate the picmicro ser ies microcontrollers on an instr uction le v el. on an y giv en instr uction, the user ma y e xamine or modify an y of the data areas or pro vide e xter nal stim ulus to an y of the pins . the input/ output r adix can be set b y the user and the e x ecution can be perf or med in; single step , e x ecute until break, or in a tr ace mode . mplab-sim fully suppor ts symbolic deb ugging using mplab-c and mp asm. the softw are sim ulator off ers the lo w cost e xibility to de v elop and deb ug code out- side of the labor ator y en vironment making it an e xcel- lent m ulti-project softw are de v elopment tool. 9.12 c compiler ( mplab-c17) the mplab-c code de v elopment system is a complete ? compiler and integ r ated de v elopment en vironment f or microchip s pic17cxxx f amily of microcontrollers . the compiler pro vides po w erful inte- g r ation capabilities and ease of use not f ound with other compilers . f or easier source le v el deb ugging, the compiler pro- vides symbol inf or mation that is compatib le with the mplab ide memor y displa y . 9.13 fuzzy logic de velopment system ( fuzzy tech-mp) fuzzy tech-mp fuzzy logic de v elopment tool is a v ail- ab le in tw o v ersions - a lo w cost introductor y v ersion, mp explorer , f or designers to gain a comprehensiv e w or king kno wledge of fuzzy logic system design; and a full-f eatured v ersion, fuzzy tech-mp , edition f or imple- menting more comple x systems . both v ersions include microchip s fuzzy lab ? demon- str ation board f or hands-on e xper ience with fuzzy logic systems implementation. 9.14 mp-drivew a y ? ?application code generator mp-dr iv ew a y is an easy-to-use windo ws-based appli- cation code gener ator . with mp-dr iv ew a y y ou can visually con gure all the per ipher als in a picmicro de vice and, with a clic k of the mouse , gener ate all the initialization and man y functional code modules in c language . the output is fully compatib le with micro- chip s mplab-c c compiler . the code produced is highly modular and allo ws easy integ r ation of y our o wn code . mp-dr iv ew a y is intelligent enough to maintain y our code through subsequent code gener ation. 9.15 seev al a ev aluation and pr ogramming system the seev al seepr om designer s kit suppor ts all microchip 2-wire and 3-wire ser ial eepr oms . the kit includes e v er ything necessar y to read, wr ite , er ase or prog r am special f eatures of an y microchip seepr om product including smar t ser ials ? and secure ser ials . the t otal endur ance ? disk is included to aid in tr ade- off analysis and reliability calculations . the total kit can signi cantly reduce time-to-mar k et and result in an optimiz ed system. 9.16 k ee l oq a ev aluation and pr ogramming t ools k ee l oq e v aluation and prog r amming tools suppor t microchips hcs secure data products . the hcs e v al- uation kit includes an lcd displa y to sho w changing codes , a decoder to decode tr ansmissions , and a pro- g r amming interf ace to prog r am test tr ansmitters .
pic16c505 ds40192a -page 54 preliminary 1998 microchip technology inc. t ab le 9-1: de velopment t ools fr om micr oc hip pic12c5xx pic16c505 pic14000 pic16c5x pic16cxxx pic16c6x pic16c7xx pic16c8x pic16c9xx pic17c4x pic17c75x 24cxx 25cxx 93cxx hcs200 hcs300 hcs301 emulator products picmaster a / picmaster-ce in-circuit emulator icepic ? low-cost in-circuit emulator software products mplab ? integrated development environment mplab ? c17 compiler fuzzy tech a -mp explorer/edition fuzzy logic dev. tool mp-driveway ? applications code generator total endurance ? software model programmers picstart a plus low-cost universal dev. kit pro mate a ii universal programmer keeloq a programmer demo boards seeval a designers kit picdem-1 picdem-2 picdem-3 keeloq a evaluation kit
1998 microchip technology inc. preliminary ds40192a -page 55 pic16c505 10.0 electrical characteristics - pic16c505 absolute maxim um ratings? ambient t emper ature under bias ........................................................................................................... ?0?c to +125?c stor age t emper ature .............................................................................................................................. ?5?c to +150?c v oltage on v dd with respect to v ss ................................................................................................................. 0 to +7.5 v v oltage on mclr with respect to v ss ............................................................................................................... 0 to +14 v v oltage on all other pins with respect to v ss ................................................................................ ?.6 v to (v dd + 0.6 v) t otal p o w er dissipation (1) ............................................................................................................................... ..... 700 mw max. current out of v ss pin ............................................................................................................................... .... 200 ma max. current into v dd pin ............................................................................................................................... ....... 150 ma input clamp current, i ik (v i < 0 or v i > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v o < 0 or v o > v dd ) ............................................................................................................ 20 ma max. output current sunk b y an y i/o pin ................................................................................................................ 25 ma max. output current sourced b y an y i/o pin ........................................................................................................... 25 ma max. output current sourced b y i/o por t ............................................................................................................. 100 ma max. output current sunk b y i/o por t .................................................................................................................. 100 ma note 1: p o w er dissipation is calculated as f ollo ws: p dis = v dd x {i dd - ? i oh } + ? {(v dd - v oh ) x i oh } + ? ( v ol x i ol ) ? no tice: stresses abo v e those listed under "maxim um ratings" ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ation listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per iods ma y aff ect de vice reliability .
pic16c505 ds40192a -page 56 preliminary 1998 microchip technology inc. 10.1 dc chara cteristics: pic16 c5 05-04 (commer cial, industrial, extended) pic16c505-20(commer cial, industrial, extended) dc characteristics p o wer suppl y pins standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) characteristic sym min t yp (1) max units conditions suppl y v olta g e v dd 3.0 4.5 5.5 5.5 v v xt , extrc , intrc and lp osc con gur a- tion h s osc con gur ation ram data retention v olta g e (2) v dr 1.5* v de vice in sleep mode v dd star t v olta g e to ensure p o wer -on reset v por v ss v see section on p o w er-on reset f or details v dd rise rate to ensure p o wer -on reset s vdd 0.05* v/ms see section on p o w er-on reset f or details suppl y current (3) i dd 1 .8 1.8 15 19 19 4.5 2 .4 2.4 27 3 5 35 16 m a ma m a m a m a m a xt and extrc options (note 4) f osc = 4 mhz, v dd = 5.5v intrc option f osc = 4 mhz, v dd = 5.5v lp o ption , commercial t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led lp o ption , industr ial t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led lp o ption , extended t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led hs o ption , industr ial t emper ature f osc = 20 mhz, v dd = 5.5v p o wer -do wn current (5) wdt enab led wdt disab led i pd 4 4 5 0.25 0.25 2 12 14 22 4 5 18 m a m a m a m a m a m a v dd = 3.0v , commercial v dd = 3.0v , industr ial v dd = 3.0v , extended v dd = 3.0v , commercial v dd = 3.0v , industr ial v dd = 3.0v , extended * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is based on char acter ization results at 25 c . this data is f or design guid- ance only and is not tested. 2: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 3: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as b us loading, oscillator type , b us r ate , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. a) the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail-to-r ail; all i/o pins tr istated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enab led/disab led as speci ed. b) f or standb y current measurements , the conditions are the same , e xcept that the de vice is in sleep mode . 4: does not include current through re xt. the current through the resistor can be estimated b y the f or m ula: i r = v dd /2re xt (ma) with re xt in kohm. 5: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is mea- sured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd or v ss .
1998 microchip technology inc. preliminary ds40192a -page 57 pic16c505 10.2 dc chara cteristics: pic16lc5 05-04 (commer cial, industrial, extended) dc characteristics p o wer suppl y pins standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) characteristic sym min t yp (1) max units conditions suppl y v olta g e v dd 3.0 2.5 5.5 5.5 v v xt , extrc , intrc osc con gur ation lp osc con gur ation ram data retention v olta g e (2) v dr 1.5* v de vice in sleep mode v dd star t v olta g e to ensure p o wer -on reset v por v ss v see section on p o w er-on reset f or details v dd rise rate to ensure p o wer -on reset s vdd 0.05* v/ms see section on p o w er-on reset f or details suppl y current (3) i dd 1 .8 1.8 15 19 19 4.5 2 .4 2.4 27 3 5 35 16 m a ma m a m a m a m a xt and extrc options (note 4) f osc = 4 mhz, v dd = 5.5v intrc option f osc = 4 mhz, v dd = 5.5v lp o ption , commercial t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led lp o ption , industr ial t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led lp o ption , extended t emper ature f osc = 32 khz, v dd = 3.0v , wdt disab led hs o ption , industr ial t emper ature f osc = 20 mhz, v dd = 5.5v p o wer -do wn current (5) wdt enab led wdt disab led i pd 4 4 5 0.25 0.25 2 12 14 22 4 5 18 m a m a m a m a m a m a v dd = 3.0v , commercial v dd = 3.0v , industr ial v dd = 3.0v , extended v dd = 3.0v , commercial v dd = 3.0v , industr ial v dd = 3.0v , extended * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is based on char acter ization results at 25 c . this data is f or design guid- ance only and is not tested. 2: this is the limit to which v dd can be lo w ered in sleep mode without losing ram data. 3: the supply current is mainly a function of the oper ating v oltage and frequency . other f actors such as b us loading, oscillator type , b us r ate , inter nal code e x ecution patter n, and temper ature also ha v e an impact on the current consumption. a) the test conditions f or all i dd measurements in activ e oper ation mode are: osc1 = e xter nal square w a v e , from r ail-to-r ail; all i/o pins tr istated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enab led/disab led as speci ed. b) f or standb y current measurements , the conditions are the same , e xcept that the de vice is in sleep mode . 4: does not include current through re xt. the current through the resistor can be estimated b y the f or m ula: i r = v dd /2re xt (ma) with re xt in kohm. 5: the po w er do wn current in sleep mode does not depend on the oscillator type . p o w er do wn current is mea- sured with the par t in sleep mode , with all i/o pins in hi-impedance state and tied to v dd or v ss .
pic16c505 ds40192a -page 58 preliminary 1998 microchip technology inc. 10.3 dc chara cteristics: pic16c505-04 (commer cial, industrial, extended) pic16c505-20(commer cial, industrial, extended) pic16lc505-04 (commer cial, industrial, extended) dc characteristics all pins except p o wer suppl y pins standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 . characteristic sym min t yp (1) max units conditions input lo w v olta g e i/o por ts mclr and rc5 (schmitt t r igger) osc1 osc1 osc1 v il v ss v ss v ss v ss v ss v ss 0.8 0.15 v dd 0.20 v dd 0.20 v dd 0.3 v dd 0.6 v dd -1.0 v v v v v v pin at hi-impedance 4.5v < v dd 5.5v pin at hi-impedance 3.0v < v dd 4.5v extrc option only (4) xt and hs options lp option input high v olta g e i/o por ts mclr and rc5 (schmitt t r igger) osc1 (schmitt t r igger) ipur v ih 0.25 v dd +0.8v 2.0 0.2 v dd +1v 0.8 v dd 0.9 v dd 0.7 v dd v dd v dd v dd v dd v dd v dd v v v v v v 2.5v < v dd 4.5v 4.5v < v dd 5.5v (5) full v dd r ange (5) full v dd r ange extrc option only (4) hs , xt and lp options input leaka g e current (2,3) i/o por ts mclr osc1 i il ? 20 ? 0.5 130 0.5 0.5 +1 250 +5 +3 m a m a m a m a f or v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v (2) v pin = v dd v ss v pin v dd , xt and lp options output lo w v olta g e i/o por ts v ol 0.6 v i ol = 8.7 ma, v dd = 4.5v output high v olta g e (3,4) i/o por ts v oh v dd ?.7 v i oh = ?.4 ma, v dd = 4.5v * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is based on char acter ization results at 25 c . this data is f or design guid- ance only and is not tested. 2: the leakage current on the mclr / v pp /rb3 pin is strongly dependent on the applied v oltage le v el. the spec- i ed le v els represent nor mal oper ating conditions . higher leakage current ma y be measured at diff erent input v oltage . 3: negativ e current is de ned as coming out of the pin. 4: f or pic16c505 de vices , the osc1/clkin pin is a schmitt t r igger input. it is not recommended that the pic16c505 be dr iv en with e xter nal cloc k in rc mode . 5: the user ma y use the better of the tw o speci cations .
1998 microchip technology inc. preliminary ds40192a -page 59 pic16c505 10.4 timing p arameter symbology and load conditions - pic 16c505 the timing par ameter symbols ha v e been created f ollo wing one of the f ollo wing f or mats: 1. tpps2pps 2. tpps t f f requency t time lo w ercase subscr ipts (pp) and their meanings: pp 2 to mc mclr c k clk out osc oscillator cy cycle time os osc1 dr t de vice reset timer t0 t0cki io i/o por t wdt w atchdog timer uppercase letters and their meanings: s f f all p p er iod h high r rise i in v alid (hi-impedance) v v alid l lo w z hi-impedance figure 10-1: load conditions - pic16c505 c l v ss pin c l = 50 pf f or all pins e xcept osc2 15 pf f or osc2 in xt , hs or lp modes when e xter nal cloc k is used to dr iv e osc1
pic16c505 ds40192a -page 60 preliminary 1998 microchip technology inc. 10.5 timing dia grams and speci cations figure 10-2: external cloc k timing - pic16c505 t ab le 10-1: external cloc k timing requirements - pic16c505 a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial), ?0 c t a +85 c (industr ial), ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions f osc exter nal clkin f requency (2) dc 4 mhz xt osc mode dc 4 mhz hs osc mode (pic16c505-04) dc 200 khz lp osc mode oscillator f requency (2) dc 4 mhz extrc osc mode 0.1 4 mhz xt osc mode 4 4 mhz hs osc mode (pic16c505-04) 4 20 mhz hs osc mode (pic16c505-20) dc 200 khz lp osc mode 1 t osc exter nal clkin p er iod (2) 250 ns xt osc mode 5 m s lp osc mode oscillator p er iod (2) 250 ns extrc osc mode 250 10,000 ns xt osc mode 250 250 ns hs ocs mode (pic16c505-04) 50 250 ns hs ocs mode (pic16c505-20) 5 m s lp osc mode 2 tcy instr uction cycle time (3) 4/f osc dc ns 200 ns tc4 = 4/fosc * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper- ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. when an e xter nal cloc k input is used, the ?ax cycle time limit is ?c (no cloc k) f or all de vices . 3: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time base per iod. osc1 q4 q1 q2 q3 q4 q1 1 3 3 4 4 2
1998 microchip technology inc. preliminary ds40192a -page 61 pic16c505 3 t osl, t osh cloc k in (osc1) lo w or high time 50* ns xt oscillator 2* m s lp oscillator 10 ns hs oscillator 4 t osr, t osf cloc k in (osc1) rise or f all time 25* ns xt oscillator 50* ns lp oscillator 15 ns hs oscillator t ab le 10-1: external cloc k timing requirements - pic16c505 (contin ued) a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial), ?0 c t a +85 c (industr ial), ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: all speci ed v alues are based on char acter ization data f or that par ticular oscillator type under standard oper- ating conditions with the de vice e x ecuting code . exceeding these speci ed limits ma y result in an unstab le oscillator oper ation and/or higher than e xpected current consumption. when an e xter nal cloc k input is used, the ?ax cycle time limit is ?c (no cloc k) f or all de vices . 3: instr uction cycle per iod ( t cy ) equals f our times the input oscillator time base per iod.
pic16c505 ds40192a -page 62 preliminary 1998 microchip technology inc. figure 10-3: i/o timing - pic16c505 t ab le 10-2: timing requirements - pic16c505 a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units 17 t osh2iov osc1 - (q1 cycle) to p or t out v alid (3) 100* ns 18 t osh2ioi osc1 - (q2 cycle) to p or t input in v alid (i/o in hold time) tbd ns 19 tiov2osh p or t input v alid to osc1 - (i/o in setup time) tbd ns 20 tior p or t output r ise time (3) 10 25** ns 21 tiof p or t output f all time (3) 10 25** ns * these par ameters are char acter iz ed b ut not tested. ** these par ameters are design targets and are not tested. no char acter ization data a v ailab le at this time . note 1: data in the t ypical (? yp? column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. 2: measurements are tak en in extrc mode . 3: see figure 10-1 f or loading conditions . osc1 i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 18 old v alue ne w v alue note: all tests m ust be done with speci ed capacitiv e loads (see data sheet) 50 pf on i/o pins and clk out . 19
1998 microchip technology inc. preliminary ds40192a -page 63 pic16c505 figure 10-4: reset, w atc hdog timer , and de vice reset timer timing - pic16c505 t ab le 10-3: reset, w atc hdog timer , and de vice reset timer - pic16c505 t ab le 10-4: dr t (de vice reset timer p eriod - pic16c505 a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 p arameter no. sym characteristic min t yp (1) max units conditions 30 tmcl mclr pulse width (lo w) 2000* ns v dd = 5 v 31 t wdt w atchdog timer time-out p er iod (no prescaler) 9* 18* 30* ms v dd = 5 v (commercial) 32 t drt de vice reset timer p er iod (2) 9* 18* 30* ms v dd = 5 v (commercial) 34 t io z i/o hi-impedance from mclr lo w 2000* ns * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25 c unless otherwise stated. these par ameters are f or design guidance only and are not tested. oscillator con guration por reset subsequent resets intrc & extrc 18 ms (typical) 300 m s (typical) xt , hs & lp 18 ms (typical) 18 ms (typical) v dd mclr inter nal por dr t timeout inter nal reset w atchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins m ust be tak en out of hi-impedance mode b y enab ling the output dr iv ers in softw are . 30 (note 2) 2: runs in mclr or wdt reset only in xt , lp and hs modes .
pic16c505 ds40192a -page 64 preliminary 1998 microchip technology inc. figure 10-5: timer0 cloc k timings - pic16c505 t ab le 10-5: timer0 cloc k requirements - pic16c505 t ab le 10-6: pull-up resistor rang es - pic16c505 a c characteristics standar d operating conditions (unless otherwise speci ed) oper ating t emper ature 0 c t a +70 c (commercial) ?0 c t a +85 c (industr ial) ?0 c t a +125 c (e xtended) oper ating v oltage v dd r ange is descr ibed in section 10.1 . p arameter no. sym characteristic min t yp (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki lo w pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki p er iod 20 or t cy + 40 * n ns whiche v er is g reater . n = prescale v alue ( 1, 2, 4, . .., 256) * these par ameters are char acter iz ed b ut not tested. note 1: data in the t ypical (? yp? column is at 5v , 25?c unless otherwise stated. these par ameters are f or design guidance only and are not tested. v dd (v olts) t emperature ( c) min t yp max units rb0/rb1/rb4 3.0 -40 27k 32k 35k w 25 33k 38k 43k w 85 33k 39k 43k w 125 37k 42k 60k w 5.5 -40 15k 17k 20k w 25 18k 20k 23k w 85 19k 22k 25k w 125 22k 24k 28k w rb3 3.0 -40 271k 326k 395k w 25 327k 390k 492k w 85 348k 427k 500k w 125 400k 472k 567k w 5.5 -40 247k 292k 360k w 25 288k 341k 437k w 85 306k 371k 448k w 125 351k 407k 500k w * these par ameters are char acter iz ed b ut not tested. t 0cki 40 41 42
1998 microchip technology inc. preliminary ds40192a -page 65 pic16c505 11.0 dc and a c characteristics - pic16c505 the g r aphs and tab les pro vided in this section are f or design guidance and are not tested or guar anteed. in some g r aphs or tab les the data presented are outside speci ed oper ating r ange (e .g., outside speci ed v dd r ange). this is f or inf or mation only and de vices will oper ate proper ly only within the speci ed r ange . the data presented in this section is a statistical summar y of data collected on units from diff erent lots o v er a per iod of time . ? ypical represents the mean of the distr ib ution while ?ax or ?in represents (mean + 3 s ) and (mean ?3 s ) respectiv ely , where s is standard de viation. figure 11-1: calibrated internal rc frequenc y rang e vs. t emperature (v dd = 5.0v) (internal rc is calibrated to 25 c, 5.0v) figure 11-2: calibrated internal rc frequenc y rang e vs. t emperature (v dd = 3.0v) (internal rc is calibrated to 25 c, 5.0v) not a v ailab le at this time . not a v ailab le at this time .
pic16c505 ds40192a -page 66 preliminary 1998 microchip technology inc. figure 11-3: internal rc frequenc y vs. calibration v alue (v dd = 5.5v) figure 11-4: int ernal rc frequenc y vs. calibration v alue (v dd = 3.5v) t ab le 11-1: dynamic i dd (typical) - wdt enab led, 25 c oscillator frequenc y v dd = 3.0v (1) v dd = 5.5v exter nal rc 4 mhz 250 m a (2) 620 m a (2) inter nal rc 4 mhz 420 m a 1.1 ma xt 4 mhz 251 m a 775 m a lp 32 khz 7 m a 37 m a hs 20 mhz n/a 4.5 ma note 1: lp oscilator based on v dd = 2.5v note 2: does not include current through e xter nal r&c . not a v ailab le at this time . not a v ailab le at this time .
1998 microchip technology inc. preliminary ds40192a -page 67 pic16c505 figure 11-5: wdt timer time-out p eriod vs . v dd 50 45 40 35 30 25 20 15 10 5 2 3 4 5 6 7 v dd (v olts) wdt per iod ( m s) max +125 c max +85 c t yp + 25 c min ? 0 c figure 11-6: s hor t d r t period vs. v dd 1000 900 800 700 600 500 400 300 200 100 2 3 4 5 6 7 v dd (v olts) wdt per iod ( m s) max +125 c max +85 c t yp + 25 c min ? 0 c
pic16c505 ds40192a -page 68 preliminary 1998 microchip technology inc. figure 11-7: i oh vs. v oh , v dd = 2.5 v figure 11-8: i oh vs. v oh , v dd = 5.5 v 500m 1.0 1.5 v oh (v olts) i oh ( ma) 2.0 2.5 0 -1 -2 -3 -4 -5 -6 -7 min +125 c max ? 0 c t yp + 25 c min +85 c 3.5 4.0 4.5 v oh (v olts) i oh ( ma) 5.0 5.5 0 -5 -10 -15 -20 -25 -30 min +125 c max ? 0 c t yp + 25 c min +85 c figure 11-9: i ol vs. v ol , v dd = 2.5 v figure 11-10: i ol vs. v ol , v dd = 5.5 v 25 20 15 10 5 0 250.0m 500.0m 1.0 v ol (v olts) i ol ( ma) min + 85 c max ? 0 c t yp + 25 c 0 min +125 c 50 40 30 20 10 0 500.0m 750.0m 1.0 v ol (v olts) i ol ( ma) 250.0m min + 85 c max ? 0 c t yp + 25 c min +125 c
1998 microchip technology inc. preliminary ds40192a -page 69 pic16c505 12.0 p ac ka ging inf ormation 12.1 p ac ka g e marking inf ormation leg end: mm...m microchip par t n umber inf or mation xx...x customer speci c inf or mation* aa y ear code (last 2 digits of calendar y ear) bb w eek code (w eek of j an uar y 1 is w eek ?1? c f acility code of the plant at which w af er is man uf actured o = outside v endor c = 5 line s = 6 line h = 8 line d mask re vision n umber e assemb ly code of the plant or countr y of or igin in which par t w as assemb led note : in the e v ent the full microchip par t n umber cannot be mar k ed on one line , it will be carr ied o v er to the ne xt line thus limiting the n umber of a v ailab le char acters f or customer speci c inf or mation. * standard o tp mar king consists of microchip par t n umber , y ear code , w eek code , f acility code , mask re v#, and assemb ly code . f or o tp mar king be y ond this , cer tain pr ice adders apply . please chec k with y our microchip sales of ce . f or qtp de vices , an y special mar king adders are included in qtp pr ice . mmmmmmmmmmmmmm xxxxxxxxxxxxxx aabbcde 14-lead pdip (300 mil) example 14-lead soic (150 mil) mmmmmmmmmm aabbcde 14-lead windo w ed cer amic side br az ed (300 mil) mmmmmmm mm example example 16c505-04i/p built 4 speed 9804saz 16c505-04i 9804saz 16c505 jw
pic16c505 ds40192a -page 70 preliminary 1998 microchip technology inc. p ac ka g e t ype: k04-005 14-lead plastic dual in-line (p) ? 300 mil n 1 2 r units inches* millimeters dimension limits min nom max min nom max pcb ro w spacing 0.300 7.62 number of pins n 14 14 pitch p 0.100 2.54 lo w er lead width b 0.013 0.018 0.023 0.33 0.46 0.58 upper lead width b1 ? 0.055 0.060 0.065 1.40 1.52 1.65 shoulder radius r 0.000 0.005 0.010 0.00 0.13 0.25 lead thic kness c 0.006 0.010 0.012 0.20 0.25 0.30 t op to seating plane a 0.120 0.145 0.170 3.05 3.68 4.32 t op of lead to seating plane a1 0.065 0.085 0.105 1.65 2.16 2.67 base to seating plane a2 0.000 0.015 0.035 0.00 0.38 0.89 tip to seating plane l 0.125 0.130 0.135 3.18 3.30 3.43 p ac kage length d 0.740 0.750 0.760 18.80 19.05 19.30 molded p ac kage width e 0.240 0.245 0.250 6.10 6.22 6.35 radius to radius width e1 0.260 0.280 0.300 6.60 7.11 7.62 ov er all ro w spacing eb 0.310 0.368 0.425 7.87 9.33 10.80 mold dr aft angle t op a 5 10 15 5 10 15 mold dr aft angle bottom b 5 10 15 5 10 15 a p a1 l b1 b a2 a c e1 b eb d e * controlling p ar ameter . ? dimension ?1 does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ?1. dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010?0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
1998 microchip technology inc. preliminary ds40192a -page 71 pic16c505 p ac ka g e t ype: k04-065 14-lead plastic small outline (sl) ? narr o w , 150 mil min dimension limits mold dr aft angle bottom mold dr aft angle t op lo w er lead width radius center line gull wing radius shoulder radius chamf er distance outside dimension molded p ac kage width molded p ac kage length shoulder height ov er all p ac k. height lead thic kness f oot angle f oot length standoff number of pins pitch b a c b ? f x a2 a1 a n p e r2 l1 l r1 e1 d units max nom min max nom 8 12 12 0.017 0.009 0 0 0.014 0.008 0.019 0.010 15 15 0.005 0.016 0.005 0.005 0.014 0.236 0.153 0.341 0.006 0.036 0.063 14 0.050 0.150 0.005 0.000 0.011 0 0.005 0.010 0.230 0.338 0.004 0.027 0.058 0.156 0.010 0.021 0.010 0.010 0.018 0.242 4 8 0.344 0.008 0.044 0.068 0.36 0.19 0 0 12 12 0.42 0.22 15 15 0.48 0.25 3.81 0.00 0.28 0.13 0.13 0.25 5.84 0 8.59 0.10 0.69 1.47 3.96 3.89 0.13 4 0.13 0.41 0.36 0.13 5.99 0.25 0.25 0.53 0.46 0.25 6.15 0.15 8.66 0.90 14 1.60 1.27 0.20 8.74 1.12 1.73 inches* millimeters n 1 2 r2 r1 d p b e1 e x l1 l c b 45 f a a1 a a2 * controlling p ar ameter . ? dimension ? does not include dam-bar protr usions . dam-bar protr usions shall not e xceed 0.003 (0.076 mm) per side or 0.006 (0.152 mm) more than dimension ? . dimensions ? and ? do not include mold ash or protr usions . mold ash or protr usions shall not e xceed 0.010 (0.254 mm) per side or 0.020 (0.508 mm) more than dimensions ? or ?.
pic16c505 ds40192a -page 72 preliminary 1998 microchip technology inc. p ac ka g e t ype: 14-lead ceramic side braz ed dual in-line with windo w (jw) ?300 mil n 1 2 0.260 0.440 0.161 0.310 0.280 0.680 0.130 0.025 0.103 0.145 0.008 0.050 0.016 0.098 min windo w diameter ov er all ro w spacing p ac kage length tip to seating plane base to seating plane t op of body to seating plane t op to seating plane upper lead width lo w er lead width pcb ro w spacing dimension limits lid length lid width p ac kage width lead thic kness number of pins pitch units t u d w eb e a2 a1 l b a c b1 p n 0.450 0.270 0.700 0.166 0.338 0.290 0.140 0.035 0.123 0.460 0.280 0.171 0.365 0.300 0.720 0.150 0.045 0.143 14 nom 0.018 0.165 0.010 0.055 0.100 0.300 max 0.185 0.012 0.060 0.020 0.102 6.86 11.43 4.22 8.57 7.37 17.78 3.56 0.89 3.12 11.18 6.60 17.27 4.09 7.87 7.11 3.30 0.64 2.62 11.68 7.11 18.29 4.34 9.27 7.62 3.81 1.14 3.63 4.19 0.25 1.40 0.46 2.54 7.62 nom millimeters min 0.41 3.68 0.20 1.27 2.49 max 14 0.51 4.70 0.30 1.52 2.59 d t e u w c eb l a1 b b1 a a2 p inches* * controlling p ar ameter .
1998 microchip technology inc. preliminary ds40192a -page 73 pic16c505 index a alu ....................................................................................... 7 applications ........................................................................... 3 architectural overview .......................................................... 7 assembler mpasm assembler ..................................................... 52 b block diagram on-chip reset circuit ................................................. 33 timer0 ......................................................................... 23 tmr0/wdt prescaler ................................................. 26 watchdog timer .......................................................... 35 brown-out protection circuit .............................................. 36 c cal0 bit .............................................................................. 16 cal1 bit .............................................................................. 16 cal2 bit .............................................................................. 16 cal3 bit .............................................................................. 16 calfst bit ......................................................................... 16 calslw bit ........................................................................ 16 carry ..................................................................................... 7 clocking scheme ................................................................ 10 code protection ............................................................ 27 , 37 configuration bits ................................................................ 27 configuration word ............................................................. 27 d dc and ac characteristics ................................................. 65 development support ......................................................... 51 development tools ............................................................. 51 device varieties .................................................................... 5 digit carry ............................................................................. 7 f family of devices pic16c505 ................................................................... 4 fsr ..................................................................................... 18 fuzzy logic dev. system ( fuzzy tech -mp) .................... 53 i i/o interfacing ..................................................................... 19 i/o ports .............................................................................. 19 i/o programming considerations ........................................ 20 icepic low-cost pic16cxxx in-circuit emulator ............ 51 id locations .................................................................. 27 , 37 indf .................................................................................... 18 indirect data addressing ..................................................... 18 instruction cycle ................................................................. 10 instruction flow/pipelining .................................................. 10 instruction set summary ..................................................... 40 k keeloq evaluation and programming tools .................... 53 l loading of pc ..................................................................... 17 m memory organization .......................................................... 11 data memory .............................................................. 12 program memory ........................................................ 11 mp-driveway - application code generator ................... 53 mplab c ............................................................................ 53 mplab integrated development environment software .... 52 o option register ............................................................... 15 osc selection ..................................................................... 27 osccal register .............................................................. 16 oscillator configurations .................................................... 28 oscillator types hs ............................................................................... 28 lp ............................................................................... 28 rc .............................................................................. 28 xt ............................................................................... 28 p package marking information ............................................. 69 packaging information ........................................................ 69 picdem-1 low-cost picmicro demo board ..................... 52 picdem-2 low-cost pic16cxx demo board ................... 52 picdem-3 low-cost pic16cxxx demo board ................ 52 picmaster in-circuit emulator ..................................... 51 picstart plus entry level development system ......... 51 por device reset timer (drt) ................................... 27 , 34 pd ............................................................................... 36 power-on reset (por) .............................................. 27 to ............................................................................... 36 portb ............................................................................... 19 power-down mode ............................................................. 37 prescaler ............................................................................ 26 pro mate ii universal programmer .............................. 51 program counter ................................................................ 17 q q cycles .............................................................................. 10 r rc oscillator ...................................................................... 29 read modify write .............................................................. 20 register file map ............................................................... 12 registers special function ......................................................... 13 reset .................................................................................. 27 reset on brown-out ........................................................... 36 s seeval evaluation and programming system .............. 53 sleep .......................................................................... 27 , 37 software simulator (mplab-sim) ...................................... 53 special features of the cpu .............................................. 27 special function registers ................................................. 13 stack ................................................................................... 17 status ................................................................................ 7 status register ............................................................... 14 t timer0 switching prescaler assignment ................................ 26 timer0 ........................................................................ 23 timer0 (tmr0) module .............................................. 23 tmr0 with external clock .......................................... 25 timing diagrams and specifications .................................. 60 timing parameter symbology and load conditions .......... 59 tris registers ................................................................... 19 w wake-up from sleep ........................................................ 37 watchdog timer (wdt) ................................................ 27 , 34 period ......................................................................... 35 programming considerations ..................................... 35 z zero bit .................................................................................. 7
pic16c505 ds40192a -page 74 preliminary 1998 microchip technology inc. notes:
1998 microchip technology inc. preliminary ds40192a -page 75 pic16c505 systems inf ormation and upgrade hot line the systems inf or mation and upg r ade line pro vides system users a listing of the latest v ersions of all of microchip's de v elopment systems softw are products . plus , this line pro vides inf or mation on ho w customers can receiv e an y currently a v ailab le upg r ade kits .the hot line numbers are: 1-800-755-2345 f or u .s . and most of canada, and 1-602-786-7302 f or the rest of the w or ld. t rademarks: the microchip name , logo , pic , picst ar t , picmaster and pr o ma te are registered tr ademar ks of microchip t echnology incor por ated in the u .s .a. and other countr ies . picmicro , fle x r om, mplab and fuzzy- lab are tr ademar ks and sqtp is a ser vice mar k of micro- chip in the u .s .a. all other tr ademar ks mentioned herein are the proper ty of their respectiv e companies . on-line suppor t microchip pro vides on-line suppor t on the microchip w or ld wide w eb (www) site . the w eb site is used b y microchip as a means to mak e les and inf or mation easily a v ailab le to customers . t o vie w the site , the user m ust ha v e access to the inter net and a w eb bro wser , such as netscape or microsoft explorer . files are also a v ailab le f or ftp do wnload from our ftp site . connecting to the micr oc hip internet w eb site the microchip w eb site is a v ailab le b y using y our f a v or ite inter net bro wser to attach to: www .micr oc hip.com the le tr ansf er site is a v ailab le b y using an ftp ser- vice to connect to: ftp://ftp.futureone .com/pub/micr oc hip the w eb site and le tr ansf er site pro vide a v ar iety of ser vices . users ma y do wnload les f or the latest de v elopment t ools , data sheets , application notes , user's guides , ar ticles and sample prog r ams . a v ar i- ety of microchip speci c b usiness inf or mation is also a v ailab le , including listings of microchip sales of ces , distr ib utors and f actor y representativ es . other data a v ailab le f or consider ation is: latest microchip press releases t echnical suppor t section with f requently ask ed questions design tips de vice err ata job p ostings microchip consultant prog r am member listing links to other useful w eb sites related to microchip products conf erences f or products , de v elopment systems , technical inf or mation and more listing of seminars and e v ents 980106
pic16c505 ds40192a -page 76 preliminary 1998 microchip technology inc. reader response it is our intention to pro vide y ou with the best documentation possib le to ensure successful use of y our microchip prod- uct. if y ou wish to pro vide y our comments on organization, clar ity , subject matter , and w a ys in which our documentation can better ser v e y ou, please f ax y our comments to the t echnical pub lications manager at (602) 786-7578. please list the f ollo wing inf or mation, and use this outline to pro vide us with y our comments about this data sheet . 1. what are the best f eatures of this document? 2. ho w does this document meet y our hardw are and softw are de v elopment needs? 3. do y ou nd the organization of this data sheet easy to f ollo w? if not, wh y? 4. what additions to the data sheet do y ou think w ould enhance the str ucture and subject? 5. what deletions from the data sheet could be made without aff ecting the o v er all usefulness? 6. is there an y incorrect or misleading inf or mation (what and where)? 7. ho w w ould y ou impro v e this document? 8. ho w w ould y ou impro v e our softw are , systems , and silicon products? t o: t echnical pub lications manager re: reader response t otal p ages sent f rom: name compan y address city / state / zip / countr y t elephone: (_______) _________ - _________ application (optional): w ould y ou lik e a reply? y n de vice: liter ature number : questions: f ax: (______) _________ - _________ ds40192a pic16c505
1998 microchip technology inc. preliminary ds40192a -page 77 pic16c505 pic16c505 pr oduct identi cation system please contact y our local sales of ce f or e xact order ing procedures . p attern: special requirements p ac ka g e: sl = 150 mil soic p = 300 mil pdip jw = 300 mil windo w ed cer amic side br az ed t emperature rang e: - = 0 c to +70 c i = -40 c to +85 c e = -40 c to +125 c frequenc y rang e: 0 4 = 4 mh z (xt , intrc , extrc osc) 04 = 200 khz (lp osc) 20 = 20 mhz (hs osc) de vice pic16c505 pic16lc505 pic16c505t (t ape & reel f or soic only) pic16lc505t (t ape & reel f or soic only) p ar t no . -xx x /xx xxx examples a) pic1 6 c50 5 -04/p commercial t emp ., pdip p ac kage , 4 mhz, nor mal v dd limits b) pic1 6 c50 5 -04i/s l industr ial t emp ., soic p ac kage , 4 mhz, nor mal v dd limits c) pic1 6 c50 5- 04i/p industr ial t emp ., pdip p ac kage , 4 m hz, nor mal v dd limits sales and suppor t products suppor ted b y a preliminar y data sheet ma y possib ly ha v e an err ata sheet descr ibing minor oper ational diff erences and recommended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: y our local microchip sales of ce (see belo w) the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277 please specify which de vice , re vision of silicon and data sheet (include liter ature #) y ou are using. f or latest v ersion inf or mation and upg r ade kits f or microchip de v elopment t ools , please call 1-800-755-2345 or 1-602-786-7302. 1. 2.
pic16c505 ds40192a -page 78 preliminary 1998 microchip technology inc. no tes:
1998 microchip technology inc. preliminary ds40192a -page 79 pic16c505 no tes:
information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip t echnology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectua l property rights arising from such use or other wise. use of microchip s products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or other wise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip t echnology inc. in the u.s.a. and other countries. all rights reser ved. all other trademarks mentioned herein are the property of their respective companies. ds40192a -page 80 ? 1998 microchip technology inc. all r ights reser v ed. ? 1998 , microchip t echnology incor por ated, usa. 4/98 pr inted on recycled paper . m americas corporate of ce microchip t echnology inc. 2355 w est chandler blvd. chandler , az 85224-6199 t el: 602-786-7200 f ax: 602-786-7277 t echnical suppor t: 602 786-7627 w eb: http://www .microchip .com atlanta microchip t echnology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el: 770-640-0034 f ax: 770-640-0307 boston microchip t echnology inc. 5 mount ro y al a v en ue mar lborough, ma 01752 t el: 508-480-9990 f ax: 508-480-8575 chica go microchip t echnology inc. 333 pierce road, suite 180 itasca, il 60143 t el: 630-285-0071 f ax: 630-285-0075 dallas microchip t echnology inc. 14651 dallas p ar kw a y , suite 816 dallas , tx 75240-8809 t el: 972-991-7177 f ax: 972-991-8588 da yton microchip t echnology inc. t w o prestige place , suite 150 miamisb urg, oh 45342 t el: 937-291-1654 f ax: 937-291-9175 los ang eles microchip t echnology inc. 18201 v on kar man, suite 1090 ir vine , ca 92612 t el: 714-263-1888 f ax: 714-263-1338 ne w y ork microchip t echnology inc. 150 motor p ar kw a y , suite 202 hauppauge , ny 11788 t el: 516-273-5305 f ax: 516-273-5335 san jose microchip t echnology inc. 2107 nor th first street, suite 590 san jose , ca 95131 t el: 408-436-7950 f ax: 408-436-7955 t or onto microchip t echnology inc. 5925 air por t road, suite 200 mississauga, ontar io l4v 1w1, canada t el: 905-405-6279 f ax: 905-405-6253 asia/p a cific hong k ong microchip asia p aci c rm 3801b , t o w er t w o metroplaza 223 hing f ong road kw ai f ong, n.t ., hong k ong t el: 852-2-401-1200 f ax: 852-2-401-3431 india microchip t echnology inc. india liaison of ce no . 6, legacy , con v ent road bangalore 560 025, india t el: 91-80-229-0061 f ax: 91-80-229-0062 japan microchip t echnology intl. inc. bene x s-1 6f 3-18-20, shin y ok ohama k ohoku-k u, y ok ohama-shi kanaga w a 222-0033 j apan t el: 81-45-471- 6166 f ax: 81-45-471-6122 k orea microchip t echnology k orea 168-1, y oungbo bldg. 3 floor samsung-dong, kangnam-k u seoul, k orea t el: 82-2-554-7200 f ax: 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden br idge bldg. 2077 y an?n road w est, hong qiao distr ict shanghai, prc 200335 t el: 86-21-6275-5700 f ax: 86 21-6275-5060 singapore microchip t echnology singapore pte ltd. 200 middle road #07-02 pr ime centre singapore 188980 t el: 65-334-8870 f ax: 65-334-8850 asia/p a cific (contin ued) t aiwan, r.o .c microchip t echnology t aiw an 10f-1c 207 t ung hua nor th road t aipei, t aiw an, r oc t el: 886-2-2717-7175 f ax: 886-2-2545-0139 eur ope united kingdom ar iz ona microchip t echnology ltd. 505 eskdale road winnersh t r iangle w okingham ber kshire , england rg41 5tu t el: 44-1189-21-5858 f ax: 44-1189-21-5835 france ar iz ona microchip t echnology sarl zone industr ielle de la bonde 2 rue du buisson aux f r aises 91300 massy , f r ance t el: 33-1-69-53-63-20 f ax: 33-1-69-30-90-79 german y ar iz ona microchip t echnology gmbh gusta v-heinemann-ring 125 d-81739 m?chen, ger man y t el: 49-89-627-144 0 f ax: 49-89-627-144-44 ital y ar iz ona microchip t echnology srl centro direzionale colleoni p alazz o t aur us 1 v . le colleoni 1 20041 ag r ate br ianza milan, italy t el: 39-39-6899939 f ax: 39-39-6899883 4/3/98 w orldwide s ales and s ervice microchip receiv ed iso 9001 quality system cer ti cation f or its w or ldwide headquar ters , design, and w af er f abr ication f acilities in j an uar y , 1997. our eld-prog r ammab le picmicro 8-bit mcus , ser ial eepr oms , related specialty memor y products and de v elopment systems conf or m to the str ingent quality standards of the inter national standard organization (iso).

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